[PATCH] D42697: [GlobalISel] Constrain the dest reg of IMPLICT_DEF

[Amara Emerson via Phabricator via llvm-commits]

aemerson updated this revision to Diff 132035.
aemerson retitled this revision from "[GlobalISel] Fix crash due to assuming a COPY src reg has a reg class" to "[GlobalISel] Constrain the dest reg of IMPLICT_DEF".
aemerson edited the summary of this revision.
aemerson added a comment.

New fix, I think the issue was that IMPLICIT_DEFs weren't constraining their dest register, while COPY selection didn't constrain the source.


Repository:
  rL LLVM

https://reviews.llvm.org/D42697

Files:
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir


Index: test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
+++ test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
@@ -5,6 +5,7 @@
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @implicit_def() { ret void }
+  define void @implicit_def_copy() { ret void }
 ...
 
 ---
@@ -25,3 +26,21 @@
     %1(s32) = G_ADD %0, %0
     %w0 = COPY %1(s32)
 ...
+---
+name:            implicit_def_copy
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: implicit_def_copy
+    ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[DEF]]
+    ; CHECK: %w0 = COPY [[COPY]]
+    %0(s32) = G_IMPLICIT_DEF
+    %1(s32) = COPY %0(s32)
+    %w0 = COPY %1(s32)
+...
Index: lib/Target/AArch64/AArch64InstructionSelector.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1407,6 +1407,12 @@
                                 : selectVaStartAAPCS(I, MF, MRI);
   case TargetOpcode::G_IMPLICIT_DEF:
     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
+    const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
+    const unsigned DstReg = I.getOperand(0).getReg();
+    const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
+    const TargetRegisterClass *DstRC =
+        getRegClassForTypeOnBank(DstTy, DstRB, RBI);
+    RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
     return true;
   }
 


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