[llvm] r323797 - [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 30 10:10:21 PST 2018


Author: rksimon
Date: Tue Jan 30 10:10:21 2018
New Revision: 323797

URL: http://llvm.org/viewvc/llvm-project?rev=323797&view=rev
Log:
[X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP

Similar to D42437, XOP supports variable shift for v16i8/v8i16/v4i32/v2i64 types.

Differential Revision: https://reviews.llvm.org/D42526

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=323797&r1=323796&r2=323797&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 30 10:10:21 2018
@@ -25593,6 +25593,11 @@ bool X86TargetLowering::isVectorShiftByS
   if (Bits == 8)
     return false;
 
+  // XOP has v16i8/v8i16/v4i32/v2i64 variable vector shifts.
+  if (Subtarget.hasXOP() && Ty->getPrimitiveSizeInBits() == 128 &&
+      (Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64))
+    return false;
+
   // AVX2 has vpsllv[dq] instructions (and other shifts) that make variable
   // shifts just as cheap as scalar ones.
   if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))

Modified: llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll?rev=323797&r1=323796&r2=323797&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll (original)
+++ llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll Tue Jan 30 10:10:21 2018
@@ -45,8 +45,7 @@ define <8 x i16> @test_16bit(<8 x i16> %
 ; CHECK-XOP:       if_true:
 ; CHECK-XOP-NEXT:    ret <8 x i16> [[MASK]]
 ; CHECK-XOP:       if_false:
-; CHECK-XOP-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
-; CHECK-XOP-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
+; CHECK-XOP-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
 ; CHECK-XOP-NEXT:    ret <8 x i16> [[RES]]
 ;
 ; CHECK-AVX2-LABEL: @test_16bit(
@@ -117,8 +116,7 @@ define <4 x i32> @test_32bit(<4 x i32> %
 ; CHECK-XOP:       if_true:
 ; CHECK-XOP-NEXT:    ret <4 x i32> [[MASK]]
 ; CHECK-XOP:       if_false:
-; CHECK-XOP-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
-; CHECK-XOP-NEXT:    [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]]
+; CHECK-XOP-NEXT:    [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
 ; CHECK-XOP-NEXT:    ret <4 x i32> [[RES]]
 ;
 ; CHECK-AVX-LABEL: @test_32bit(
@@ -158,8 +156,7 @@ define <2 x i64> @test_64bit(<2 x i64> %
 ; CHECK-XOP:       if_true:
 ; CHECK-XOP-NEXT:    ret <2 x i64> [[MASK]]
 ; CHECK-XOP:       if_false:
-; CHECK-XOP-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <2 x i32> zeroinitializer
-; CHECK-XOP-NEXT:    [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]]
+; CHECK-XOP-NEXT:    [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
 ; CHECK-XOP-NEXT:    ret <2 x i64> [[RES]]
 ;
 ; CHECK-AVX-LABEL: @test_64bit(




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