[PATCH] D42353: [Codegen] support of 'nof' flag lowering on X86 target

[Mohammed Agabaria via Phabricator via llvm-commits]

magabari marked 2 inline comments as done.
magabari added a comment.

fixed craig notes



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Comment at: CodeGen/SelectionDAG/LegalizeVectorOps.cpp:755
+  if (!TLI.isOperationLegalOrCustom(ISD::FDIV, DstVT)) {
+    EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts / 2);
+    DstVT = EVT::getVectorVT(*DAG.getContext(), FloatVT, NumElts);
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craig.topper wrote:
> What guarantees HalfVT is a legal type for the target?
In fact I did this only because as you may notice that i use wider FP types (i32 goes to f64), I assume that when we get to this function the original integer vector type is legal, so if I enlarge the FP type it may be not legal anymore. because of that i did the split.
but in any case i think that Type legalizer should take care of that if HalfVT still not legal.


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Comment at: Target/X86/X86ISelLowering.cpp:38113
+  // we prefer this only in case of AVX2\AVX512 
+  return (Subtarget.hasAVX2() || Subtarget.hasAVX512());
+}    
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craig.topper wrote:
> hasAVX2 implies hasAVX512. But what's special about AVX2 here?
fixed.
We have measured this optimization in AVX2 and AVX512 and it gives good speedups but in SSE that may not be the optimized way to do that so we return false.


Repository:
  rL LLVM

https://reviews.llvm.org/D42353