[PATCH] D41771: [mips] Include EVA instructions in the Std2MicroMips mapping tables

[Simon Dardis via Phabricator via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM.

During review, I spotted that the left/right eva stores and loads are not in the instruction mapping tables and that they have incorrect DAG patterns associated with them but that can be submitted as a separate patch.



================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:786-796
+    def LHE_MM  : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, II_LHE>,
                   POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
-    def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>,
+    def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>,
                   POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
-    def LWE_MM  : LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>,
+    def LWE_MM  : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>,
                   POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
+    def SBE_MM  : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, II_SBE>,
----------------
Nit: These lines are overly long.


================
Comment at: test/CodeGen/Mips/micromips-eva.mir:211-212
+
+# CHECK: 60 41 a6 05   cachee  2, 5($1)
+# CHECK: 60 41 a4 05   prefe 2, 5($1)
----------------
Nit: align the instruction text with the other instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D41771