[llvm] r323631 - [X86] Make foldLogicOfSetCCs work better for vectors pre legal types/operations

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Jan 28 23:52:55 2018
New Revision: 323631

URL: http://llvm.org/viewvc/llvm-project?rev=323631&view=rev
Log:
[X86] Make foldLogicOfSetCCs work better for vectors pre legal types/operations

Summary:
There's a check in the code to only check getSetCCResultType after LegalOperations or if the type is MVT::i1. But the i1 check is only allowing scalar types through. I think it should check that the scalar type is MVT::i1 so that it will work for vectors.

The changed test already does this combine with AVX512VL where getSetCCResultType returns vXi1. But with avx512f and no VLX getSetCCResultType returns a type matching the width of the input type.

Reviewers: spatel, RKSimon

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42619

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=323631&r1=323630&r2=323631&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jan 28 23:52:55 2018
@@ -3525,7 +3525,7 @@ SDValue DAGCombiner::foldLogicOfSetCCs(b
   // operations on the left and right operands, so those types must match.
   EVT VT = N0.getValueType();
   EVT OpVT = LL.getValueType();
-  if (LegalOperations || VT != MVT::i1)
+  if (LegalOperations || VT.getScalarType() != MVT::i1)
     if (VT != getSetCCResultType(OpVT))
       return SDValue();
   if (OpVT != RL.getValueType())

Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll?rev=323631&r1=323630&r2=323631&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll Sun Jan 28 23:52:55 2018
@@ -1132,10 +1132,8 @@ define <8 x i32> @testnm_and(<8 x i32> %
 ; NoVLX:       # %bb.0:
 ; NoVLX-NEXT:    # kill: def %ymm3 killed %ymm3 def %zmm3
 ; NoVLX-NEXT:    # kill: def %ymm2 killed %ymm2 def %zmm2
-; NoVLX-NEXT:    # kill: def %ymm1 killed %ymm1 def %zmm1
-; NoVLX-NEXT:    # kill: def %ymm0 killed %ymm0 def %zmm0
+; NoVLX-NEXT:    vpor %ymm1, %ymm0, %ymm0
 ; NoVLX-NEXT:    vptestnmd %zmm0, %zmm0, %k1
-; NoVLX-NEXT:    vptestnmd %zmm1, %zmm1, %k1 {%k1}
 ; NoVLX-NEXT:    vpblendmd %zmm2, %zmm3, %zmm0 {%k1}
 ; NoVLX-NEXT:    # kill: def %ymm0 killed %ymm0 killed %zmm0
 ; NoVLX-NEXT:    retq