[llvm] r323592 - Regenrate test results for avx-brcond.ll . NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 27 08:44:00 PST 2018
Author: deadalnix
Date: Sat Jan 27 08:44:00 2018
New Revision: 323592
URL: http://llvm.org/viewvc/llvm-project?rev=323592&view=rev
Log:
Regenrate test results for avx-brcond.ll . NFC
Modified:
llvm/trunk/test/CodeGen/X86/avx-brcond.ll
Modified: llvm/trunk/test/CodeGen/X86/avx-brcond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-brcond.ll?rev=323592&r1=323591&r2=323592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-brcond.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-brcond.ll Sat Jan 27 08:44:00 2018
@@ -1,17 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
declare i32 @llvm.x86.avx.ptestz.256(<4 x i64> %p1, <4 x i64> %p2) nounwind
declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind
define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test1:
-; CHECK: vptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: jne LBB0_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI0_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB0_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI0_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = icmp ne i32 %res, 0
+ %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = icmp ne i32 %res, 0
br i1 %one, label %bb1, label %bb2
bb1:
@@ -28,14 +37,22 @@ return:
}
define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test3:
-; CHECK: vptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: jne LBB1_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI1_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB1_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI1_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = trunc i32 %res to i1
+ %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = trunc i32 %res to i1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -52,14 +69,22 @@ return:
}
define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test4:
-; CHECK: vptest
-; CHECK-NEXT: jae
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: jae LBB2_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI2_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB2_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI2_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = icmp ne i32 %res, 0
+ %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = icmp ne i32 %res, 0
br i1 %one, label %bb1, label %bb2
bb1:
@@ -76,14 +101,22 @@ return:
}
define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test6:
-; CHECK: vptest
-; CHECK-NEXT: jae
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: jae LBB3_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI3_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB3_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI3_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = trunc i32 %res to i1
+ %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = trunc i32 %res to i1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -100,14 +133,22 @@ return:
}
define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test7:
-; CHECK: vptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: jne LBB4_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI4_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB4_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI4_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = icmp eq i32 %res, 1
+ %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = icmp eq i32 %res, 1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -124,14 +165,22 @@ return:
}
define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test8:
-; CHECK: vptest
-; CHECK-NEXT: je
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: vptest %ymm0, %ymm0
+; CHECK-NEXT: je LBB5_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: vaddps LCPI5_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB5_2: ## %bb2
+; CHECK-NEXT: vdivps LCPI5_0, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
- %one = icmp ne i32 %res, 1
+ %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind
+ %one = icmp ne i32 %res, 1
br i1 %one, label %bb1, label %bb2
bb1:
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