[llvm] r323585 - [TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of vXi1 vectors into logic ops.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 27 01:10:58 PST 2018
Author: ctopper
Date: Sat Jan 27 01:10:58 2018
New Revision: 323585
URL: http://llvm.org/viewvc/llvm-project?rev=323585&view=rev
Log:
[TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of vXi1 vectors into logic ops.
This transform was already being done for setcc of scalar i1. This extends it to vectors.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=323585&r1=323584&r2=323585&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jan 27 01:10:58 2018
@@ -2282,50 +2282,52 @@ SDValue TargetLowering::SimplifySetCC(EV
// Fold away ALL boolean setcc's.
SDValue Temp;
- if (N0.getValueType() == MVT::i1 && foldBooleans) {
+ if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
+ EVT OpVT = N0.getValueType();
switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
- Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
- N0 = DAG.getNOT(dl, Temp, MVT::i1);
+ Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
+ N0 = DAG.getNOT(dl, Temp, OpVT);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
- N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, OpVT);
+ N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, OpVT);
+ N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, OpVT);
+ N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, OpVT);
+ N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
break;
}
- if (VT != MVT::i1) {
+ if (VT.getScalarType() != MVT::i1) {
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(N0.getNode());
// FIXME: If running after legalize, we probably can't do this.
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
+ ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
+ N0 = DAG.getNode(ExtendCode, dl, VT, N0);
}
return N0;
}
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=323585&r1=323584&r2=323585&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Sat Jan 27 01:10:58 2018
@@ -502,9 +502,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4
; KNL-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
; KNL-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
; KNL-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
-; KNL-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; KNL-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; KNL-NEXT: kandnw %k0, %k1, %k1
+; KNL-NEXT: vpcmpleq %zmm1, %zmm0, %k1 {%k1}
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; KNL-NEXT: vzeroupper
@@ -512,9 +511,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4
;
; SKX-LABEL: test4:
; SKX: ## %bb.0:
-; SKX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
; SKX-NEXT: vpcmpgtq %ymm3, %ymm2, %k1
-; SKX-NEXT: kandnw %k0, %k1, %k0
+; SKX-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1}
; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
@@ -525,9 +523,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4
; AVX512BW-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
; AVX512BW-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
; AVX512BW-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
-; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; AVX512BW-NEXT: kandnw %k0, %k1, %k1
+; AVX512BW-NEXT: vpcmpleq %zmm1, %zmm0, %k1 {%k1}
; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512BW-NEXT: vzeroupper
@@ -539,9 +536,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4
; AVX512DQ-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
; AVX512DQ-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
; AVX512DQ-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
-; AVX512DQ-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; AVX512DQ-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; AVX512DQ-NEXT: kandnw %k0, %k1, %k0
+; AVX512DQ-NEXT: vpcmpleq %zmm1, %zmm0, %k0 {%k1}
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512DQ-NEXT: vzeroupper
@@ -560,9 +556,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2
; KNL-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
; KNL-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
-; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
-; KNL-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; KNL-NEXT: kandnw %k1, %k0, %k1
+; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
+; KNL-NEXT: vpcmpleq %zmm3, %zmm2, %k1 {%k1}
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; KNL-NEXT: vzeroupper
@@ -570,9 +565,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2
;
; SKX-LABEL: test5:
; SKX: ## %bb.0:
-; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k0
-; SKX-NEXT: vpcmpgtq %xmm3, %xmm2, %k1
-; SKX-NEXT: kandnw %k1, %k0, %k0
+; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k1
+; SKX-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1}
; SKX-NEXT: vpmovm2q %k0, %xmm0
; SKX-NEXT: retq
;
@@ -582,9 +576,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2
; AVX512BW-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
; AVX512BW-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
-; AVX512BW-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
-; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; AVX512BW-NEXT: kandnw %k1, %k0, %k1
+; AVX512BW-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
+; AVX512BW-NEXT: vpcmpleq %zmm3, %zmm2, %k1 {%k1}
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512BW-NEXT: vzeroupper
@@ -596,9 +589,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2
; AVX512DQ-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
; AVX512DQ-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
-; AVX512DQ-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
-; AVX512DQ-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
-; AVX512DQ-NEXT: kandnw %k1, %k0, %k0
+; AVX512DQ-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
+; AVX512DQ-NEXT: vpcmpleq %zmm3, %zmm2, %k0 {%k1}
; AVX512DQ-NEXT: vpmovm2q %k0, %zmm0
; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512DQ-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=323585&r1=323584&r2=323585&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Sat Jan 27 01:10:58 2018
@@ -7031,18 +7031,16 @@ entry:
define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1) {
; GENERIC-LABEL: test4:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 # sched: [3:1.00]
; GENERIC-NEXT: vpcmpgtq %ymm3, %ymm2, %k1 # sched: [3:1.00]
-; GENERIC-NEXT: kandnw %k0, %k1, %k0 # sched: [1:1.00]
+; GENERIC-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1} # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2d %k0, %xmm0 # sched: [1:0.33]
; GENERIC-NEXT: vzeroupper # sched: [100:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test4:
; SKX: # %bb.0:
-; SKX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 # sched: [3:1.00]
; SKX-NEXT: vpcmpgtq %ymm3, %ymm2, %k1 # sched: [3:1.00]
-; SKX-NEXT: kandnw %k0, %k1, %k0 # sched: [1:1.00]
+; SKX-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1} # sched: [3:1.00]
; SKX-NEXT: vpmovm2d %k0, %xmm0 # sched: [1:0.25]
; SKX-NEXT: vzeroupper # sched: [4:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
@@ -7056,17 +7054,15 @@ define <4 x i32> @test4(<4 x i64> %x, <4
define <2 x i64> @vcmp_test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1) {
; GENERIC-LABEL: vcmp_test5:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 # sched: [3:1.00]
-; GENERIC-NEXT: vpcmpgtq %xmm3, %xmm2, %k1 # sched: [3:1.00]
-; GENERIC-NEXT: kandnw %k1, %k0, %k0 # sched: [1:1.00]
+; GENERIC-NEXT: vpcmpgtq %xmm0, %xmm1, %k1 # sched: [3:1.00]
+; GENERIC-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1} # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2q %k0, %xmm0 # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vcmp_test5:
; SKX: # %bb.0:
-; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 # sched: [3:1.00]
-; SKX-NEXT: vpcmpgtq %xmm3, %xmm2, %k1 # sched: [3:1.00]
-; SKX-NEXT: kandnw %k1, %k0, %k0 # sched: [1:1.00]
+; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k1 # sched: [3:1.00]
+; SKX-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1} # sched: [3:1.00]
; SKX-NEXT: vpmovm2q %k0, %xmm0 # sched: [1:0.25]
; SKX-NEXT: retq # sched: [7:1.00]
%x_gt_y = icmp slt <2 x i64> %x, %y
Modified: llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=323585&r1=323584&r2=323585&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll Sat Jan 27 01:10:58 2018
@@ -543,7 +543,8 @@ define <16 x i1> @interleaved_load_vf16_
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vpcmpeqb %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
+; AVX1-NEXT: vpxor %xmm0, %xmm3, %xmm0
+; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -591,7 +592,8 @@ define <16 x i1> @interleaved_load_vf16_
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; AVX2-NEXT: vpcmpeqb %xmm0, %xmm4, %xmm0
-; AVX2-NEXT: vpcmpeqb %xmm0, %xmm2, %xmm0
+; AVX2-NEXT: vpxor %xmm0, %xmm2, %xmm0
+; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -660,97 +662,98 @@ define <16 x i1> @interleaved_load_vf16_
define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
; AVX1-LABEL: interleaved_load_vf32_i8_stride4:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %ymm10
-; AVX1-NEXT: vmovdqa 32(%rdi), %ymm13
+; AVX1-NEXT: vmovdqa (%rdi), %ymm11
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm14
; AVX1-NEXT: vmovdqa 64(%rdi), %ymm2
; AVX1-NEXT: vmovdqa 96(%rdi), %ymm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = <u,u,u,u,0,4,8,12,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm11
-; AVX1-NEXT: vpshufb %xmm6, %xmm11, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm12
+; AVX1-NEXT: vpshufb %xmm6, %xmm12, %xmm5
; AVX1-NEXT: vpshufb %xmm6, %xmm3, %xmm7
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm12
-; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm13
+; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm4
; AVX1-NEXT: vpshufb %xmm0, %xmm2, %xmm5
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm7[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm8
-; AVX1-NEXT: vextractf128 $1, %ymm13, %xmm14
-; AVX1-NEXT: vpshufb %xmm6, %xmm14, %xmm5
-; AVX1-NEXT: vpshufb %xmm6, %xmm13, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm14, %xmm15
+; AVX1-NEXT: vpshufb %xmm6, %xmm15, %xmm5
+; AVX1-NEXT: vpshufb %xmm6, %xmm14, %xmm6
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
-; AVX1-NEXT: vextractf128 $1, %ymm10, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm11, %xmm6
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm4
-; AVX1-NEXT: vpshufb %xmm0, %xmm10, %xmm0
+; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm0
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm5[4,5,6,7]
; AVX1-NEXT: vblendps {{.*#+}} ymm8 = ymm0[0,1,2,3],ymm8[4,5,6,7]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm4
+; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm4
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm5
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm5, %xmm12, %xmm1
+; AVX1-NEXT: vpshufb %xmm5, %xmm13, %xmm1
; AVX1-NEXT: vpshufb %xmm5, %xmm2, %xmm7
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
-; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm4
-; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm0
+; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm4
+; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm4
-; AVX1-NEXT: vpshufb %xmm5, %xmm10, %xmm5
+; AVX1-NEXT: vpshufb %xmm5, %xmm11, %xmm5
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vblendps {{.*#+}} ymm9 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm1
+; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm1
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm4
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm4, %xmm12, %xmm5
+; AVX1-NEXT: vpshufb %xmm4, %xmm13, %xmm5
; AVX1-NEXT: vpshufb %xmm4, %xmm2, %xmm7
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
-; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm5
-; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm0
+; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm5
+; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; AVX1-NEXT: vpshufb %xmm4, %xmm6, %xmm5
-; AVX1-NEXT: vpshufb %xmm4, %xmm10, %xmm4
+; AVX1-NEXT: vpshufb %xmm4, %xmm11, %xmm4
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
+; AVX1-NEXT: vblendps {{.*#+}} ymm10 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
+; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm1
+; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm3
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
+; AVX1-NEXT: vpshufb %xmm3, %xmm13, %xmm4
+; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
+; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm2
+; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm2
+; AVX1-NEXT: vpshufb %xmm3, %xmm11, %xmm3
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm1, %xmm11, %xmm4
-; AVX1-NEXT: vpshufb %xmm1, %xmm3, %xmm3
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
-; AVX1-NEXT: vpshufb %xmm4, %xmm12, %xmm5
-; AVX1-NEXT: vpshufb %xmm4, %xmm2, %xmm2
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
-; AVX1-NEXT: vpshufb %xmm1, %xmm14, %xmm3
-; AVX1-NEXT: vpshufb %xmm1, %xmm13, %xmm1
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
-; AVX1-NEXT: vpshufb %xmm4, %xmm6, %xmm3
-; AVX1-NEXT: vpshufb %xmm4, %xmm10, %xmm4
-; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
-; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
+; AVX1-NEXT: vextractf128 $1, %ymm9, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm2
+; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpcmpeqb %xmm9, %xmm8, %xmm2
-; AVX1-NEXT: vextractf128 $1, %ymm9, %xmm3
-; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm4
-; AVX1-NEXT: vpcmpeqb %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm4
-; AVX1-NEXT: vpcmpeqb %xmm4, %xmm2, %xmm2
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm10, %xmm3
+; AVX1-NEXT: vpcmpeqb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpeqb %xmm0, %xmm10, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vxorps %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: interleaved_load_vf32_i8_stride4:
@@ -845,7 +848,8 @@ define <32 x i1> @interleaved_load_vf32_
; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3,4,5],ymm2[6,7]
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqb %ymm0, %ymm8, %ymm0
+; AVX2-NEXT: vpxor %ymm0, %ymm8, %ymm0
+; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: interleaved_load_vf32_i8_stride4:
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