[PATCH] D42599: [AArch64] Fix BITCAST lowering crash

[Evandro Menezes via Phabricator via llvm-commits]

evandro created this revision.
evandro added reviewers: t.p.northover, MatzeB.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar, rengolin, aemerson.

The data type is assumed to be a vector, but sometimes it may not be, leading to an assertion.

Add simple test-case to verify this.


Repository:
  rL LLVM

https://reviews.llvm.org/D42599

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/strqu.ll


Index: llvm/test/CodeGen/AArch64/strqu.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/strqu.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu    | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu    -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,SPLIT %s
+
+; CHECK-LABEL: test_split_f:
+; NOSPLIT: str q{{[0-9]+}}, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2s }, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2s }, [x{{[0-9]+}}]
+define void @test_split_f(<4 x float> %val, <4 x float>* %addr) {
+  store <4 x float> %val, <4 x float>* %addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: test_split_d:
+; NOSPLIT: str q{{[0-9]+}}, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2d }, [x{{[0-9]+}}]
+define void @test_split_d(<2 x double> %val, <2 x double>* %addr) {
+  store <2 x double> %val, <2 x double>* %addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: test_split_128:
+; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}]
+define void @test_split_128(fp128 %val, fp128* %addr) {
+  store fp128 %val, fp128* %addr, align 8
+  ret void
+}
+
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8742,7 +8742,8 @@
   // If the source type has twice the number of elements as our destination
   // type, we know this is an extract of the high or low half of the vector.
   EVT SVT = Source->getValueType(0);
-  if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
+  if (!SVT.isVector() ||
+      SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
     return SDValue();
 
   DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");


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