[llvm] r323540 - [X86][SSE] Drop PMADDWD in lowerMul
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 08:57:36 PST 2018
Author: rksimon
Date: Fri Jan 26 08:57:36 2018
New Revision: 323540
URL: http://llvm.org/viewvc/llvm-project?rev=323540&view=rev
Log:
[X86][SSE] Drop PMADDWD in lowerMul
As mentioned in D42258, we don't need this any more
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=323540&r1=323539&r2=323540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 26 08:57:36 2018
@@ -22262,13 +22262,6 @@ static SDValue LowerMUL(SDValue Op, cons
assert(Subtarget.hasSSE2() && !Subtarget.hasSSE41() &&
"Should not custom lower when pmulld is available!");
- // If the upper 17 bits of each element are zero then we can use PMADDWD.
- APInt Mask17 = APInt::getHighBitsSet(32, 17);
- if (DAG.MaskedValueIsZero(A, Mask17) && DAG.MaskedValueIsZero(B, Mask17))
- return DAG.getNode(X86ISD::VPMADDWD, dl, VT,
- DAG.getBitcast(MVT::v8i16, A),
- DAG.getBitcast(MVT::v8i16, B));
-
// Extract the odd parts.
static const int UnpackMask[] = { 1, -1, 3, -1 };
SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
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