[PATCH] D42308: [X86][SSE] Don't colaesce v4i32 extracts (RFC)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D42308#989014, @niravd wrote:

> This seems reasonable to me. The test outputs all look better or more optimizable (Have you looked at why the ands aren't being colleasced into a vector?)


Thanks - we do have x86 lowering code the vectorizes BUILDVECTOR(X & C1, Y & C2, .....) -> BUILDVECTOR(X, Y, ...) & BUILDVECTOR(C1, C2, ...) but nothing that does the reverse even though both are often generated during legalization. I'm always a bit afraid of doing too much vectorization code in the DAG.


Repository:
  rL LLVM

https://reviews.llvm.org/D42308