[llvm] r323527 - [AMDGPU][MC] Enabled disassembler for image atomic operations
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 06:07:38 PST 2018
Author: dpreobra
Date: Fri Jan 26 06:07:38 2018
New Revision: 323527
URL: http://llvm.org/viewvc/llvm-project?rev=323527&view=rev
Log:
[AMDGPU][MC] Enabled disassembler for image atomic operations
See bug 35988: https://bugs.llvm.org/show_bug.cgi?id=35988
Differential Revision: https://reviews.llvm.org/D42186
Reviewers: vpykhtin, artem.tamazov, arsenm
Modified:
llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td?rev=323527&r1=323526&r2=323527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td Fri Jan 26 06:07:38 2018
@@ -136,12 +136,14 @@ multiclass MIMG_Store <bits<7> op, strin
}
class MIMG_Atomic_Helper <string asm, RegisterClass data_rc,
- RegisterClass addr_rc> : MIMG_Helper <
+ RegisterClass addr_rc, string dns="",
+ bit enableDasm = 0> : MIMG_Helper <
(outs data_rc:$vdst),
(ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
- asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"> {
+ asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da",
+ !if(enableDasm, dns, "")> {
let mayLoad = 1;
let mayStore = 1;
let hasSideEffects = 1; // FIXME: Remove this
@@ -152,43 +154,45 @@ class MIMG_Atomic_Helper <string asm, Re
}
class MIMG_Atomic_Real_si<mimg op, string name, string asm,
- RegisterClass data_rc, RegisterClass addr_rc> :
- MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
+ RegisterClass data_rc, RegisterClass addr_rc, bit enableDasm> :
+ MIMG_Atomic_Helper<asm, data_rc, addr_rc, "SICI", enableDasm>,
SIMCInstr<name, SIEncodingFamily.SI>,
MIMGe<op.SI> {
let isCodeGenOnly = 0;
let AssemblerPredicates = [isSICI];
- let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class MIMG_Atomic_Real_vi<mimg op, string name, string asm,
- RegisterClass data_rc, RegisterClass addr_rc> :
- MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
+ RegisterClass data_rc, RegisterClass addr_rc, bit enableDasm> :
+ MIMG_Atomic_Helper<asm, data_rc, addr_rc, "VI", enableDasm>,
SIMCInstr<name, SIEncodingFamily.VI>,
MIMGe<op.VI> {
let isCodeGenOnly = 0;
let AssemblerPredicates = [isVI];
- let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
multiclass MIMG_Atomic_Helper_m <mimg op, string name, string asm,
- RegisterClass data_rc, RegisterClass addr_rc> {
+ RegisterClass data_rc,
+ RegisterClass addr_rc,
+ bit enableDasm = 0> {
let isPseudo = 1, isCodeGenOnly = 1 in {
def "" : MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
SIMCInstr<name, SIEncodingFamily.NONE>;
}
let ssamp = 0 in {
- def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc>;
+ def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc, enableDasm>;
- def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc>;
+ def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc, enableDasm>;
}
}
multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> {
- defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32>;
+ // _V* variants have different address size, but the size is not encoded.
+ // So only one variant can be disassembled. V1 looks the safest to decode.
+ defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32, 1>;
defm _V2 : MIMG_Atomic_Helper_m <op, asm # "_V2", asm, data_rc, VReg_64>;
defm _V4 : MIMG_Atomic_Helper_m <op, asm # "_V3", asm, data_rc, VReg_128>;
}
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt?rev=323527&r1=323526&r2=323527&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt Fri Jan 26 06:07:38 2018
@@ -1,5 +1,9 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -check-prefix=VI %s
+#===------------------------------------------------------------------------===#
+# Image load/store
+#===------------------------------------------------------------------------===#
+
# VI: image_load v[0:3], v4, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x04,0x00,0x02,0x00]
0x00 0x1f 0x00 0xf0 0x04 0x00 0x02 0x00
@@ -37,3 +41,31 @@
# VI: image_load v255, v0, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x00,0xf0,0x00,0xff,0x00,0x00]
0x00 0x13 0x00 0xf0 0x00 0xff 0x00 0x00
+
+#===------------------------------------------------------------------------===#
+# Image atomics
+#===------------------------------------------------------------------------===#
+
+# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_atomic_add v252, v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
+0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00
+
+# VI: image_atomic_add v5, v255, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00]
+0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00
+
+# VI: image_atomic_add v5, v1, s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
+0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00
+
+# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
+0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00
+
+# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00
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