[llvm] r323521 - [MIR] Add support for addrspace in MIR
Francis Visoiu Mistrih via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 03:47:28 PST 2018
Author: thegameg
Date: Fri Jan 26 03:47:28 2018
New Revision: 323521
URL: http://llvm.org/viewvc/llvm-project?rev=323521&view=rev
Log:
[MIR] Add support for addrspace in MIR
Add support for printing / parsing the addrspace of a MachineMemOperand.
Fixes PR35970.
Differential Revision: https://reviews.llvm.org/D42502
Added:
llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
Modified:
llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll
llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Fri Jan 26 03:47:28 2018
@@ -242,6 +242,7 @@ static MIToken::TokenKind getIdentifierK
.Case("dereferenceable", MIToken::kw_dereferenceable)
.Case("invariant", MIToken::kw_invariant)
.Case("align", MIToken::kw_align)
+ .Case("addrspace", MIToken::kw_addrspace)
.Case("stack", MIToken::kw_stack)
.Case("got", MIToken::kw_got)
.Case("jump-table", MIToken::kw_jump_table)
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Fri Jan 26 03:47:28 2018
@@ -93,6 +93,7 @@ struct MIToken {
kw_non_temporal,
kw_invariant,
kw_align,
+ kw_addrspace,
kw_stack,
kw_got,
kw_jump_table,
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Fri Jan 26 03:47:28 2018
@@ -228,6 +228,7 @@ public:
Optional<unsigned> &TiedDefIdx);
bool parseOffset(int64_t &Offset);
bool parseAlignment(unsigned &Alignment);
+ bool parseAddrspace(unsigned &Addrspace);
bool parseOperandsOffset(MachineOperand &Op);
bool parseIRValue(const Value *&V);
bool parseMemoryOperandFlag(MachineMemOperand::Flags &Flags);
@@ -2094,6 +2095,17 @@ bool MIParser::parseAlignment(unsigned &
return false;
}
+bool MIParser::parseAddrspace(unsigned &Addrspace) {
+ assert(Token.is(MIToken::kw_addrspace));
+ lex();
+ if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isSigned())
+ return error("expected an integer literal after 'addrspace'");
+ if (getUnsigned(Addrspace))
+ return true;
+ lex();
+ return false;
+}
+
bool MIParser::parseOperandsOffset(MachineOperand &Op) {
int64_t Offset = 0;
if (parseOffset(Offset))
@@ -2405,6 +2417,10 @@ bool MIParser::parseMachineMemoryOperand
if (parseAlignment(BaseAlignment))
return true;
break;
+ case MIToken::kw_addrspace:
+ if (parseAddrspace(Ptr.AddrSpace))
+ return true;
+ break;
case MIToken::md_tbaa:
lex();
if (parseMDNode(AAInfo.TBAA))
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Fri Jan 26 03:47:28 2018
@@ -892,6 +892,8 @@ void MIPrinter::print(const LLVMContext
OS << ", !range ";
Op.getRanges()->printAsOperand(OS, MST);
}
+ if (unsigned AS = Op.getAddrSpace())
+ OS << ", addrspace " << AS;
OS << ')';
}
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Jan 26 03:47:28 2018
@@ -457,7 +457,7 @@ define void @trunc(i64 %a) {
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
-; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
+; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42, addrspace 42)
; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
@@ -480,7 +480,7 @@ define i64 @load(i64* %addr, i64 addrspa
; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY %x2
; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY %x3
; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16)
-; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42)
+; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42, addrspace 42)
; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr)
; CHECK: RET_ReallyLR
define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2) {
Modified: llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir Fri Jan 26 03:47:28 2018
@@ -321,7 +321,7 @@ body: |
---
# CHECK-LABEL: name: optimize_if_and_saveexec_xor_valu_middle
# CHECK: %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
-# CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET %vgpr0, undef %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into `i32 addrspace(1)* undef`)
+# CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET %vgpr0, undef %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
# CHECK-NEXT: %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
# CHECK-NEXT: %exec = COPY killed %sgpr2_sgpr3
# CHECK-NEXT: SI_MASK_BRANCH
Modified: llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll Fri Jan 26 03:47:28 2018
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: syncscopes
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
define void @syncscopes(
i32 %agent,
i32 addrspace(4)* %agent_out,
Added: llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir?rev=323521&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir Fri Jan 26 03:47:28 2018
@@ -0,0 +1,31 @@
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+
+--- |
+
+ define void @addrspace_memoperands() {
+ ret void
+ }
+
+...
+---
+name: addrspace_memoperands
+body: |
+ bb.0:
+
+ ; CHECK-LABEL: name: addrspace_memoperands
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, addrspace 1)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 2, addrspace 3)
+ ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store 8, addrspace 1)
+ ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4, align 2, addrspace 3)
+ ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4)
+ ; CHECK: RET_ReallyLR
+ %0:_(p0) = COPY %x0
+ %1:_(s64) = G_LOAD %0(p0) :: (load 8, addrspace 1)
+ %2:_(s32) = G_LOAD %0(p0) :: (load 4, align 2, addrspace 3)
+ G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1)
+ G_STORE %2(s32), %0(p0) :: (store 4, align 2, addrspace 3)
+ ; addrspace 0 is accepted by the parser but not printed
+ G_STORE %2(s32), %0(p0) :: (store 4, addrspace 0)
+ RET_ReallyLR
+...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir?rev=323521&r1=323520&r2=323521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir Fri Jan 26 03:47:28 2018
@@ -42,9 +42,9 @@
!0 = !{i32 1}
# GCN-LABEL: name: syncscopes
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out)
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
...
---
name: syncscopes
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