[PATCH] D42533: [X86FixupBWInsts] Fix miscompilation if sibling sub-register is live.

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added inline comments.


================
Comment at: lib/Target/X86/X86FixupBWInsts.cpp:256
+    if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
+        TRI->checkRegistersAlias(SuperDestReg, MO.getReg()))
+      return false;
----------------
andrew.w.kaylor wrote:
> Wouldn't  TRI->isSuperOrSubRegisterEq() have the same effect as TRI->checkRegistersAlias()? It isn't clear to me why the new function is needed.
> 
> Also, a comment here saying more verbosely what this is meant to be looking for would be helpful. I'm thinking something like this:
> 
> ```
> // If MO is a use of any part of the destination register but is not equal to OrigDestReg
> // or one of its subregisters, we cannot use SuperDestReg. For example, if OrigDestReg
> // is  %al then an implicit use of %ah, %ax, %eax, or %rax will prevent us from using
> // the %eax register.
> ```
There is also TargetRegisterInfo::regsOverlap() which should be slightly more efficient (this is implemented in CodeGen because we have access to register units theres, which the MC layer doesn't know about)


================
Comment at: test/CodeGen/X86/fixup-bw-inst.mir:204-246
+
+---
+# CHECK-LABEL: name: test5
+name:            test5
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
----------------
https://llvm.org/docs/MIRLangRef.html#simplifying-mir-files


Repository:
  rL LLVM

https://reviews.llvm.org/D42533