[llvm] r323452 - [Hexagon] SETEQ and SETNE are valid integer condition codes

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Jan 25 10:07:27 2018
New Revision: 323452

URL: http://llvm.org/viewvc/llvm-project?rev=323452&view=rev
Log:
[Hexagon] SETEQ and SETNE are valid integer condition codes

Added:
    llvm/trunk/test/CodeGen/Hexagon/vect/setcc-v2i32.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=323452&r1=323451&r2=323452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Thu Jan 25 10:07:27 2018
@@ -1289,7 +1289,8 @@ SDValue HexagonTargetLowering::LowerSETC
   EVT RHSVT = RHS.getValueType();
 
   if (LHSVT == MVT::v2i16) {
-    assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
+    assert(CC == ISD::SETEQ || CC == ISD::SETNE ||
+           ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
     unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
                                                 : ISD::ZERO_EXTEND;
     SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);

Added: llvm/trunk/test/CodeGen/Hexagon/vect/setcc-v2i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/setcc-v2i32.ll?rev=323452&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/setcc-v2i32.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/setcc-v2i32.ll Thu Jan 25 10:07:27 2018
@@ -0,0 +1,21 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; REQUIRES: asserts
+
+; Check that this testcase doesn't crash.
+; CHECK: vcmpw.eq
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define i32 @fred(<2 x i16>* %a0) #0 {
+b1:
+  %v2 = load <2 x i16>, <2 x i16>* %a0, align 2
+  %v3 = icmp eq <2 x i16> %v2, zeroinitializer
+  %v4 = zext <2 x i1> %v3 to <2 x i16>
+  %v5 = extractelement <2 x i16> %v4, i32 1
+  %v8 = icmp ne i16 %v5, 1
+  %v9 = zext i1 %v8 to i32
+  ret i32 %v9
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }