[PATCH] D42356: [AArch64] Implement dynamic stack probing for windows

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo added a comment.

In https://reviews.llvm.org/D42356#986541, @aemerson wrote:

> For GlobalISel we haven't had to have very target specific code in the IRTranslator for this before. @qcolombet any opinion on whether we want to include target/ABI specific code into the IRTranslator? My feeling is that we want to avoid this, the alternative I can see is to introduce a new opcode for G_DYNALLOCA and lower that at isel.


Using a new opcode that maps down to this case here probably sounds like the best option.



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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7452
+
+  SDValue Callee = DAG.getTargetExternalSymbol("__chkstk", PtrVT, 0);
+
----------------
aemerson wrote:
> Unfortunately it seems we need to pass a const char* to this because of lifetime issues at codegen. Do you have any ideas on how to do this better?
I don't think I'm following what the issue is here? Right now I'm passing "__chkstk" as a const char* here. Do you mean further, if refactoring this into a form that also suits darwin, with a different function name? In that case, the method providing the function name could probably just return const char* as well, instead of e.g. a StringRef.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7458
+
+  Size = DAG.getNode(ISD::SRL, dl, MVT::i64, Size,
+                     DAG.getConstant(4, dl, MVT::i64));
----------------
aemerson wrote:
> Can you separate this out into some kind of helper for the Windows specific ABI?
I can try to make it easier fit in the darwin version from D40863, by more clearly separating out the windows specific bits.


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Comment at: test/CodeGen/AArch64/win64_vararg.ll:171
+; CHECK: sub     x20, x8, x15, lsl #4
 ; CHECK: mov     sp, x20
 ; CHECK: ldur    x21, [x29, #-40]
----------------
This form produces the pattern of "mov x8, sp; sub x20, x8, x15, lsl #4; mov sp x20", when it could just as well do "sub sp, sp, x15, lsl #4; mov x20, sp" - however I didn't manage to make the code in AArch64ISelLowering do that - any hints?

The version I did in D41131 for the fixed stack parts use BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP).addReg(AArch64::SP, RegState::Kill).addReg(AArch64::X15, RegState::Kill).addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 4)) - which achieves exactly what I want.


Repository:
  rL LLVM

https://reviews.llvm.org/D42356