[PATCH] D42502: [MIR] Add support for addrspace in MIR

[Matthias Braun via Phabricator via llvm-commits]

MatzeB accepted this revision.
MatzeB added subscribers: arsenm, tstellar.
MatzeB added a comment.
This revision is now accepted and ready to land.

LGTM

(+CC AMDGPU so they can veto if they don't like the syntax)



================
Comment at: test/CodeGen/MIR/AArch64/addrspace-memoperands.mir:26
+    G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1)
+    G_STORE %2(s32), %0(p0) :: (store 4, align 2, addrspace 3)
+    RET_ReallyLR
----------------
Can you add a line that `addrspace 0` is correctly parsed (and not printed)


https://reviews.llvm.org/D42502