[llvm] r323374 - [Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jan 24 13:19:51 2018
New Revision: 323374

URL: http://llvm.org/viewvc/llvm-project?rev=323374&view=rev
Log:
[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code

The code in EmitFunctionEntryCode needs to know the maximum stack
alignment, but it runs very early in the selection process (before
lowering). The final stack alignment may change during lowering, so
the code needs to be moved to where the alignment is known.


Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=323374&r1=323373&r2=323374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Wed Jan 24 13:19:51 2018
@@ -1034,6 +1034,23 @@ void HexagonDAGToDAGISel::ppHoistZextI1(
   }
 }
 
+void HexagonDAGToDAGISel::ppEmitAligna() {
+  auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
+  auto &HFI = *HST.getFrameLowering();
+  if (!HFI.needsAligna(*MF))
+    return;
+
+  MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineBasicBlock &EntryBB = MF->front();
+  unsigned AR = FuncInfo->CreateReg(MVT::i32);
+  unsigned MaxA = MFI.getMaxAlignment();
+  MachineBasicBlock::iterator End = EntryBB.end();
+  DebugLoc DL = EntryBB.findDebugLoc(End);
+  BuildMI(EntryBB, End, DL, HII->get(Hexagon::PS_aligna), AR)
+      .addImm(MaxA);
+  MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
+}
+
 void HexagonDAGToDAGISel::PreprocessISelDAG() {
   // Repack all nodes before calling each preprocessing function,
   // because each of them can modify the set of nodes.
@@ -1089,21 +1106,11 @@ void HexagonDAGToDAGISel::PreprocessISel
       CurDAG->dump();
     });
   }
-}
-
-void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
-  auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
-  auto &HFI = *HST.getFrameLowering();
-  if (!HFI.needsAligna(*MF))
-    return;
 
-  MachineFrameInfo &MFI = MF->getFrameInfo();
-  MachineBasicBlock *EntryBB = &MF->front();
-  unsigned AR = FuncInfo->CreateReg(MVT::i32);
-  unsigned MaxA = MFI.getMaxAlignment();
-  BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
-      .addImm(MaxA);
-  MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
+  // Finally, emit the PS_aligna instruction, if necessary. Do it late,
+  // because the max required stack layout may change up until right before
+  // instruction selection.
+  ppEmitAligna();
 }
 
 // Match a frame index that can be used in an addressing mode.

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h?rev=323374&r1=323373&r2=323374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h Wed Jan 24 13:19:51 2018
@@ -51,8 +51,6 @@ public:
     return true;
   }
   void PreprocessISelDAG() override;
-  void EmitFunctionEntryCode() override;
-
   void Select(SDNode *N) override;
 
   // Complex Pattern Selectors.
@@ -139,6 +137,7 @@ private:
   void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
   void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
   void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
+  void ppEmitAligna();
 
   SmallDenseMap<SDNode *,int> RootWeights;
   SmallDenseMap<SDNode *,int> RootHeights;