[llvm] r323354 - [ARM] Expand long shifts for Thumb1 to __aeabi_ calls

[Weiming Zhao via llvm-commits]

Author: weimingz
Date: Wed Jan 24 10:00:57 2018
New Revision: 323354

URL: http://llvm.org/viewvc/llvm-project?rev=323354&view=rev
Log:
[ARM] Expand long shifts for Thumb1 to __aeabi_ calls

Summary: For long shifts, the inlined version takes about 20 instructions on Thumb1. To avoid the code bloat, expand to __aeabi_ calls if target is Thumb1.

Reviewers: samparker

Reviewed By: samparker

Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42401

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/shift-i64.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=323354&r1=323353&r2=323354&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jan 24 10:00:57 2018
@@ -820,6 +820,13 @@ ARMTargetLowering::ARMTargetLowering(con
   setOperationAction(ISD::SRA,       MVT::i64, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
 
+  // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
+  if (Subtarget->isThumb1Only()) {
+    setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+    setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+    setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+  }
+
   setOperationAction(ISD::ADDC,      MVT::i32, Custom);
   setOperationAction(ISD::ADDE,      MVT::i32, Custom);
   setOperationAction(ISD::SUBC,      MVT::i32, Custom);

Modified: llvm/trunk/test/CodeGen/ARM/shift-i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/shift-i64.ll?rev=323354&r1=323353&r2=323354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/shift-i64.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/shift-i64.ll Wed Jan 24 10:00:57 2018
@@ -1,7 +1,9 @@
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix=EXPAND
 
 define i64 @test_shl(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_shl:
+; EXPAND-LABEL: test_shl:
   ; First calculate the hi part when the shift amount is small enough that it
   ; contains components from both halves. It'll be returned in r1 so that's a
   ; reasonable place for it to end up.
@@ -22,6 +24,9 @@ define i64 @test_shl(i64 %val, i64 %amt)
 ; CHECK: lsl r0, r0, r2
 ; CHECK: movge r0, #0
 
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_llsl
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = shl i64 %val, %amt
   ret i64 %res
 }
@@ -29,6 +34,7 @@ define i64 @test_shl(i64 %val, i64 %amt)
 ; Explanation for lshr is pretty much the reverse of shl.
 define i64 @test_lshr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_lshr:
+; EXPAND-LABEL: test_lshr:
 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
 ; CHECK: lsr r0, r0, r2
 ; CHECK: orr r0, r0, r1, lsl [[REVERSE_SHIFT]]
@@ -37,6 +43,10 @@ define i64 @test_lshr(i64 %val, i64 %amt
 ; CHECK: lsrge r0, r1, [[EXTRA_SHIFT]]
 ; CHECK: lsr r1, r1, r2
 ; CHECK: movge r1, #0
+
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_llsr
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = lshr i64 %val, %amt
   ret i64 %res
 }
@@ -45,6 +55,7 @@ define i64 @test_lshr(i64 %val, i64 %amt
 ; amount is large to get the right sign bit.
 define i64 @test_ashr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_ashr:
+; EXPAND-LABEL: test_ashr:
 ; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
 ; CHECK: asr [[HI_TMP:.*]], r1, r2
 ; CHECK: lsr r0, r0, r2
@@ -54,6 +65,10 @@ define i64 @test_ashr(i64 %val, i64 %amt
 ; CHECK: asrge [[HI_TMP]], r1, #31
 ; CHECK: asrge r0, r1, [[EXTRA_SHIFT]]
 ; CHECK: mov r1, [[HI_TMP]]
+
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_lasr
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = ashr i64 %val, %amt
   ret i64 %res
 }