[PATCH] D42479: DAGCombiner: Combine SDIV with non-splat vector pow2 divider

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

How bad does the codegen get if we don't limit this to targets with vector shifts? Again, thinking AVX1 (Jaguar) here., but combine_vec_sdiv_by_pow2b_v4i64 looks like a missed opportunity



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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2932
+    return true;
+  };
   // fold (sdiv X, pow2) -> simple ops after legalize
----------------
Did you look at using matchBinaryPredicate here?


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2970
+      C1 = DAG.getBuildVector(VT, DL, Ops1);
+    }
 
----------------
You can probably get the getNode/FoldConstantArithmetic methods to do most of this for you?


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Comment at: lib/Target/X86/X86ISelLowering.cpp:22738
+bool X86TargetLowering::isSupportedVectorVarShift(EVT VT, unsigned Opcode) const {
+  if (!VT.isSimple())
+    return false;
----------------
If we're going to expose this then ideally we'd allow isSupportedVectorVarShift to flag XOP vector shifts as supported (and fast), but the original SupportedVectorVarShift usage below prevented us as we have to call custom lowering to X86ISD::VPSHA/VPSHL.

Also, there is a lot of crossover with isVectorShiftByScalarCheap.


Repository:
  rL LLVM

https://reviews.llvm.org/D42479