[compiler-rt] r323315 - [builtins] Align addresses to cache lines in __clear_cache for aarch64

[Martin Storsjo via llvm-commits]

Author: mstorsjo
Date: Wed Jan 24 02:14:52 2018
New Revision: 323315

URL: http://llvm.org/viewvc/llvm-project?rev=323315&view=rev
Log:
[builtins] Align addresses to cache lines in __clear_cache for aarch64

This makes sure that the last cache line gets invalidated properly.

This matches the example code at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html,
and also matches what libgcc does.

Differential Revision: https://reviews.llvm.org/D42196

Modified:
    compiler-rt/trunk/lib/builtins/clear_cache.c

Modified: compiler-rt/trunk/lib/builtins/clear_cache.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/builtins/clear_cache.c?rev=323315&r1=323314&r2=323315&view=diff
==============================================================================
--- compiler-rt/trunk/lib/builtins/clear_cache.c (original)
+++ compiler-rt/trunk/lib/builtins/clear_cache.c Wed Jan 24 02:14:52 2018
@@ -163,12 +163,14 @@ void __clear_cache(void *start, void *en
    * uintptr_t in case this runs in an IPL32 environment.
    */
   const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
-  for (addr = xstart; addr < xend; addr += dcache_line_size)
+  for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
+       addr += dcache_line_size)
     __asm __volatile("dc cvau, %0" :: "r"(addr));
   __asm __volatile("dsb ish");
 
   const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
-  for (addr = xstart; addr < xend; addr += icache_line_size)
+  for (addr = xstart & ~(icache_line_size - 1); addr < xend;
+       addr += icache_line_size)
     __asm __volatile("ic ivau, %0" :: "r"(addr));
   __asm __volatile("isb sy");
 #elif defined (__powerpc64__)