[PATCH] D42437: X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
Zvi Rackover via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 23 17:38:23 PST 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL323292: X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW (authored by zvi, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D42437
Files:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
Index: llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
===================================================================
--- llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
+++ llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
@@ -29,16 +29,34 @@
}
define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
-; CHECK-LABEL: @test_16bit(
-; CHECK-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
-; CHECK-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
-; CHECK: if_true:
-; CHECK-NEXT: ret <8 x i16> [[MASK]]
-; CHECK: if_false:
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
-; CHECK-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
-; CHECK-NEXT: ret <8 x i16> [[RES]]
-;
+; CHECK-SSE2-LABEL: @test_16bit
+; CHECK-SSE2: if_true:
+; CHECK-SSE2-NOT: shufflevector
+; CHECK-SSE2: if_false:
+; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-SSE2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX2-LABEL: @test_16bit
+; CHECK-AVX2: if_true:
+; CHECK-AVX2-NOT: shufflevector
+; CHECK-AVX2: if_false:
+; CHECK-AVX2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-XOP-LABEL: @test_16bit
+; CHECK-XOP: if_true:
+; CHECK-XOP-NOT: shufflevector
+; CHECK-XOP: if_false:
+; CHECK-XOP: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-XOP: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX512BW-LABEL: @test_16bit
+; CHECK-AVX512BW: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX512BW: if_true:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: if_false:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: shl <8 x i16> %lhs, [[SPLAT]]
%mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
br i1 %tst, label %if_true, label %if_false
Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
@@ -25681,6 +25681,10 @@
if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))
return false;
+ // AVX512BW has shifts such as vpsllvw.
+ if (Subtarget.hasBWI() && Bits == 16)
+ return false;
+
// Otherwise, it's significantly cheaper to shift by a scalar amount than by a
// fully general vector.
return true;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D42437.131180.patch
Type: text/x-patch
Size: 2532 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180124/27c4c820/attachment.bin>
More information about the llvm-commits
mailing list