[llvm] r323261 - [X86] Move 'Int_' to the end of the name of the VCOMISS/VUCOMISS and instructions to get them picked up by the scheduler model regexs.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 23 13:37:51 PST 2018
Author: ctopper
Date: Tue Jan 23 13:37:51 2018
New Revision: 323261
URL: http://llvm.org/viewvc/llvm-project?rev=323261&view=rev
Log:
[X86] Move 'Int_' to the end of the name of the VCOMISS/VUCOMISS and instructions to get them picked up by the scheduler model regexs.
All other intrinsic instructions put the _Int on the end. This make these instructions consistent and gets the prefix instregexs in the scheduler models to pick them up.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Jan 23 13:37:51 2018
@@ -7655,19 +7655,19 @@ let Defs = [EFLAGS], Predicates = [HasAV
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
}
let isCodeGenOnly = 1 in {
- defm Int_VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
- sse_load_f32, "ucomiss", SSE_COMIS>, PS, EVEX, VEX_LIG,
- EVEX_CD8<32, CD8VT1>;
- defm Int_VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem,
- sse_load_f64, "ucomisd", SSE_COMIS>, PD, EVEX,
- VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
+ defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
+ sse_load_f32, "ucomiss", SSE_COMIS>, PS, EVEX, VEX_LIG,
+ EVEX_CD8<32, CD8VT1>;
+ defm VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem,
+ sse_load_f64, "ucomisd", SSE_COMIS>, PD, EVEX,
+ VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
- defm Int_VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem,
- sse_load_f32, "comiss", SSE_COMIS>, PS, EVEX, VEX_LIG,
- EVEX_CD8<32, CD8VT1>;
- defm Int_VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem,
- sse_load_f64, "comisd", SSE_COMIS>, PD, EVEX,
- VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
+ defm VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem,
+ sse_load_f32, "comiss", SSE_COMIS>, PS, EVEX, VEX_LIG,
+ EVEX_CD8<32, CD8VT1>;
+ defm VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem,
+ sse_load_f64, "comisd", SSE_COMIS>, PD, EVEX,
+ VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Jan 23 13:37:51 2018
@@ -563,6 +563,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::CMP32rr, X86::CMP32rm, 0 },
{ X86::CMP64rr, X86::CMP64rm, 0 },
{ X86::CMP8rr, X86::CMP8rm, 0 },
+ { X86::COMISDrr_Int, X86::COMISDrm_Int, TB_NO_REVERSE },
+ { X86::COMISSrr_Int, X86::COMISSrm_Int, TB_NO_REVERSE },
{ X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_NO_REVERSE },
{ X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
{ X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
@@ -595,10 +597,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
{ X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
{ X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
- { X86::Int_COMISDrr, X86::Int_COMISDrm, TB_NO_REVERSE },
- { X86::Int_COMISSrr, X86::Int_COMISSrm, TB_NO_REVERSE },
- { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, TB_NO_REVERSE },
- { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, TB_NO_REVERSE },
{ X86::MOV16rr, X86::MOV16rm, 0 },
{ X86::MOV32rr, X86::MOV32rm, 0 },
{ X86::MOV64rr, X86::MOV64rm, 0 },
@@ -672,7 +670,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE },
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
{ X86::UCOMISDrr, X86::UCOMISDrm, 0 },
+ { X86::UCOMISDrr_Int, X86::UCOMISDrm_Int, TB_NO_REVERSE },
{ X86::UCOMISSrr, X86::UCOMISSrm, 0 },
+ { X86::UCOMISSrr_Int, X86::UCOMISSrm_Int, TB_NO_REVERSE },
// MMX version of foldable instructions
{ X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, TB_ALIGN_16 },
@@ -696,10 +696,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::PSWAPDrr, X86::PSWAPDrm, 0 },
// AVX 128-bit versions of foldable instructions
- { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, TB_NO_REVERSE },
- { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, TB_NO_REVERSE },
- { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, TB_NO_REVERSE },
- { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, TB_NO_REVERSE },
+ { X86::VCOMISDrr_Int, X86::VCOMISDrm_Int, TB_NO_REVERSE },
+ { X86::VCOMISSrr_Int, X86::VCOMISSrm_Int, TB_NO_REVERSE },
{ X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
{ X86::VCVTTSD2SI64rr_Int,X86::VCVTTSD2SI64rm_Int,TB_NO_REVERSE },
{ X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
@@ -769,7 +767,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VTESTPDrr, X86::VTESTPDrm, 0 },
{ X86::VTESTPSrr, X86::VTESTPSrm, 0 },
{ X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
+ { X86::VUCOMISDrr_Int, X86::VUCOMISDrm_Int, TB_NO_REVERSE },
{ X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
+ { X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE },
// AVX 256-bit foldable instructions
{ X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jan 23 13:37:51 2018
@@ -2277,13 +2277,13 @@ multiclass sse12_ord_cmp_int<bits<8> opc
ValueType vt, Operand memop,
ComplexPattern mem_cpat, string OpcodeStr,
OpndItins itins> {
- def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
+ def rr_Int: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
[(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
itins.rr>,
Sched<[itins.Sched]>;
let mayLoad = 1 in
- def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, memop:$src2),
+ def rm_Int: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, memop:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
[(set EFLAGS, (OpNode (vt RC:$src1),
mem_cpat:$src2))],
@@ -2304,15 +2304,15 @@ let Defs = [EFLAGS] in {
}
let isCodeGenOnly = 1 in {
- defm Int_VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
- sse_load_f32, "ucomiss", SSE_COMIS>, PS, VEX, VEX_WIG;
- defm Int_VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
- sse_load_f64, "ucomisd", SSE_COMIS>, PD, VEX, VEX_WIG;
-
- defm Int_VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
- sse_load_f32, "comiss", SSE_COMIS>, PS, VEX, VEX_WIG;
- defm Int_VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
- sse_load_f64, "comisd", SSE_COMIS>, PD, VEX, VEX_WIG;
+ defm VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
+ sse_load_f32, "ucomiss", SSE_COMIS>, PS, VEX, VEX_WIG;
+ defm VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
+ sse_load_f64, "ucomisd", SSE_COMIS>, PD, VEX, VEX_WIG;
+
+ defm VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
+ sse_load_f32, "comiss", SSE_COMIS>, PS, VEX, VEX_WIG;
+ defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
+ sse_load_f64, "comisd", SSE_COMIS>, PD, VEX, VEX_WIG;
}
defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
"ucomiss", SSE_COMIS>, PS;
@@ -2327,14 +2327,14 @@ let Defs = [EFLAGS] in {
}
let isCodeGenOnly = 1 in {
- defm Int_UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
- sse_load_f32, "ucomiss", SSE_COMIS>, PS;
- defm Int_UCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
- sse_load_f64, "ucomisd", SSE_COMIS>, PD;
-
- defm Int_COMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
- sse_load_f32, "comiss", SSE_COMIS>, PS;
- defm Int_COMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
+ defm UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
+ sse_load_f32, "ucomiss", SSE_COMIS>, PS;
+ defm UCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
+ sse_load_f64, "ucomisd", SSE_COMIS>, PD;
+
+ defm COMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
+ sse_load_f32, "comiss", SSE_COMIS>, PS;
+ defm COMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
sse_load_f64, "comisd", SSE_COMIS>, PD;
}
} // Defs = [EFLAGS]
Modified: llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir (original)
+++ llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir Tue Jan 23 13:37:51 2018
@@ -2276,22 +2276,22 @@ body: |
%xmm0 = VMOVQI2PQIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVZPQILo2PQIrr %xmm0
%xmm0 = VMOVZPQILo2PQIZrr %xmm0
- ; CHECK: Int_VCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VCOMISDrr %xmm0, %xmm1, implicit-def %eflags
- Int_VCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
- ; CHECK: Int_VCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VCOMISSrr %xmm0, %xmm1, implicit-def %eflags
- Int_VCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
- ; CHECK: Int_VUCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VUCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VUCOMISDrr %xmm0, %xmm1, implicit-def %eflags
- Int_VUCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
- ; CHECK: Int_VUCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VUCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags
- Int_VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
+ ; CHECK: VCOMISDrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VCOMISDZrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VCOMISDrr_Int %xmm0, %xmm1, implicit-def %eflags
+ VCOMISDZrr_Int %xmm0, %xmm1, implicit-def %eflags
+ ; CHECK: VCOMISSrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VCOMISSZrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VCOMISSrr_Int %xmm0, %xmm1, implicit-def %eflags
+ VCOMISSZrr_Int %xmm0, %xmm1, implicit-def %eflags
+ ; CHECK: VUCOMISDrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VUCOMISDZrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VUCOMISDrr_Int %xmm0, %xmm1, implicit-def %eflags
+ VUCOMISDZrr_Int %xmm0, %xmm1, implicit-def %eflags
+ ; CHECK: VUCOMISSrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VUCOMISSZrm_Int %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VUCOMISSrr_Int %xmm0, %xmm1, implicit-def %eflags
+ VUCOMISSZrr_Int %xmm0, %xmm1, implicit-def %eflags
; CHECK: VCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISDrr %xmm0, %xmm1, implicit-def %eflags
@@ -4596,22 +4596,22 @@ body: |
%xmm16 = VMOVQI2PQIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVZPQILo2PQIZrr %xmm16
%xmm16 = VMOVZPQILo2PQIZrr %xmm16
- ; CHECK: Int_VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
- Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
- ; CHECK: Int_VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
- Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
- ; CHECK: Int_VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
- Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
- ; CHECK: Int_VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- Int_VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
- ; CHECK: Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
- Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
+ ; CHECK: VCOMISDZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VCOMISDZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VCOMISDZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ VCOMISDZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ ; CHECK: VCOMISSZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VCOMISSZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VCOMISSZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ VCOMISSZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ ; CHECK: VUCOMISDZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VUCOMISDZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VUCOMISDZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ VUCOMISDZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ ; CHECK: VUCOMISSZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ VUCOMISSZrm_Int %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
+ ; CHECK: VUCOMISSZrr_Int %xmm16, %xmm1, implicit-def %eflags
+ VUCOMISSZrr_Int %xmm16, %xmm1, implicit-def %eflags
; CHECK: VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Tue Jan 23 13:37:51 2018
@@ -447,11 +447,11 @@ declare <4 x float> @llvm.x86.sse.cmp.ss
define i32 @test_comiss(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
; GENERIC-LABEL: test_comiss:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: comiss %xmm1, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: comiss %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %cl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %cl # sched: [1:0.33]
-; GENERIC-NEXT: comiss (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: comiss (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %dl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -489,11 +489,11 @@ define i32 @test_comiss(<4 x float> %a0,
;
; SANDY-LABEL: test_comiss:
; SANDY: # %bb.0:
-; SANDY-NEXT: vcomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SANDY-NEXT: vcomiss %xmm1, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %cl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %cl # sched: [1:0.33]
-; SANDY-NEXT: vcomiss (%rdi), %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vcomiss (%rdi), %xmm0 # sched: [8:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %dl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -531,11 +531,11 @@ define i32 @test_comiss(<4 x float> %a0,
;
; SKYLAKE-LABEL: test_comiss:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vcomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT: vcomiss %xmm1, %xmm0 # sched: [2:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT: vcomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vcomiss (%rdi), %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -545,11 +545,11 @@ define i32 @test_comiss(<4 x float> %a0,
;
; SKX-LABEL: test_comiss:
; SKX: # %bb.0:
-; SKX-NEXT: vcomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vcomiss %xmm1, %xmm0 # sched: [2:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %cl # sched: [1:0.50]
; SKX-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKX-NEXT: vcomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vcomiss (%rdi), %xmm0 # sched: [7:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %dl # sched: [1:0.50]
; SKX-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -3383,11 +3383,11 @@ define float @test_subss(float %a0, floa
define i32 @test_ucomiss(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
; GENERIC-LABEL: test_ucomiss:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: ucomiss %xmm1, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: ucomiss %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %cl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %cl # sched: [1:0.33]
-; GENERIC-NEXT: ucomiss (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: ucomiss (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %dl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -3425,11 +3425,11 @@ define i32 @test_ucomiss(<4 x float> %a0
;
; SANDY-LABEL: test_ucomiss:
; SANDY: # %bb.0:
-; SANDY-NEXT: vucomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SANDY-NEXT: vucomiss %xmm1, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %cl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %cl # sched: [1:0.33]
-; SANDY-NEXT: vucomiss (%rdi), %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vucomiss (%rdi), %xmm0 # sched: [8:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %dl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -3467,11 +3467,11 @@ define i32 @test_ucomiss(<4 x float> %a0
;
; SKYLAKE-LABEL: test_ucomiss:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vucomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT: vucomiss %xmm1, %xmm0 # sched: [2:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT: vucomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vucomiss (%rdi), %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -3481,11 +3481,11 @@ define i32 @test_ucomiss(<4 x float> %a0
;
; SKX-LABEL: test_ucomiss:
; SKX: # %bb.0:
-; SKX-NEXT: vucomiss %xmm1, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vucomiss %xmm1, %xmm0 # sched: [2:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %cl # sched: [1:0.50]
; SKX-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKX-NEXT: vucomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vucomiss (%rdi), %xmm0 # sched: [7:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %dl # sched: [1:0.50]
; SKX-NEXT: andb %al, %dl # sched: [1:0.25]
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=323261&r1=323260&r2=323261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Tue Jan 23 13:37:51 2018
@@ -522,11 +522,11 @@ declare <2 x double> @llvm.x86.sse2.cmp.
define i32 @test_comisd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_comisd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: comisd %xmm1, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: comisd %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %cl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %cl # sched: [1:0.33]
-; GENERIC-NEXT: comisd (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: comisd (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %dl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -564,11 +564,11 @@ define i32 @test_comisd(<2 x double> %a0
;
; SANDY-LABEL: test_comisd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SANDY-NEXT: vcomisd %xmm1, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %cl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %cl # sched: [1:0.33]
-; SANDY-NEXT: vcomisd (%rdi), %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vcomisd (%rdi), %xmm0 # sched: [8:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %dl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -606,11 +606,11 @@ define i32 @test_comisd(<2 x double> %a0
;
; SKYLAKE-LABEL: test_comisd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT: vcomisd %xmm1, %xmm0 # sched: [2:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT: vcomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vcomisd (%rdi), %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -620,11 +620,11 @@ define i32 @test_comisd(<2 x double> %a0
;
; SKX-LABEL: test_comisd:
; SKX: # %bb.0:
-; SKX-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vcomisd %xmm1, %xmm0 # sched: [2:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %cl # sched: [1:0.50]
; SKX-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKX-NEXT: vcomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vcomisd (%rdi), %xmm0 # sched: [7:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %dl # sched: [1:0.50]
; SKX-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -9040,11 +9040,11 @@ define double @test_subsd(double %a0, do
define i32 @test_ucomisd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_ucomisd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: ucomisd %xmm1, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: ucomisd %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %cl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %cl # sched: [1:0.33]
-; GENERIC-NEXT: ucomisd (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: ucomisd (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: setnp %al # sched: [1:0.50]
; GENERIC-NEXT: sete %dl # sched: [1:0.50]
; GENERIC-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -9082,11 +9082,11 @@ define i32 @test_ucomisd(<2 x double> %a
;
; SANDY-LABEL: test_ucomisd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vucomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SANDY-NEXT: vucomisd %xmm1, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %cl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %cl # sched: [1:0.33]
-; SANDY-NEXT: vucomisd (%rdi), %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vucomisd (%rdi), %xmm0 # sched: [8:1.00]
; SANDY-NEXT: setnp %al # sched: [1:0.50]
; SANDY-NEXT: sete %dl # sched: [1:0.50]
; SANDY-NEXT: andb %al, %dl # sched: [1:0.33]
@@ -9124,11 +9124,11 @@ define i32 @test_ucomisd(<2 x double> %a
;
; SKYLAKE-LABEL: test_ucomisd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vucomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT: vucomisd %xmm1, %xmm0 # sched: [2:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT: vucomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vucomisd (%rdi), %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
@@ -9138,11 +9138,11 @@ define i32 @test_ucomisd(<2 x double> %a
;
; SKX-LABEL: test_ucomisd:
; SKX: # %bb.0:
-; SKX-NEXT: vucomisd %xmm1, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vucomisd %xmm1, %xmm0 # sched: [2:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %cl # sched: [1:0.50]
; SKX-NEXT: andb %al, %cl # sched: [1:0.25]
-; SKX-NEXT: vucomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vucomisd (%rdi), %xmm0 # sched: [7:1.00]
; SKX-NEXT: setnp %al # sched: [1:0.50]
; SKX-NEXT: sete %dl # sched: [1:0.50]
; SKX-NEXT: andb %al, %dl # sched: [1:0.25]
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