[llvm] r323215 - [x86] Reautogenerate a bunch of tests for D42287. NFC
Alexander Ivchenko via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 23 08:08:16 PST 2018
Author: aivchenk
Date: Tue Jan 23 08:08:15 2018
New Revision: 323215
URL: http://llvm.org/viewvc/llvm-project?rev=323215&view=rev
Log:
[x86] Reautogenerate a bunch of tests for D42287. NFC
Modified:
llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll Tue Jan 23 08:08:15 2018
@@ -32,7 +32,7 @@ define i64 @test_ret_i64() {
define i8 @test_arg_i8(i8 %a) {
; X32-LABEL: test_arg_i8:
; X32: # %bb.0:
-; X32-NEXT: movb 4(%esp), %al
+; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: retl
;
; X64-LABEL: test_arg_i8:
@@ -45,7 +45,7 @@ define i8 @test_arg_i8(i8 %a) {
define i16 @test_arg_i16(i16 %a) {
; X32-LABEL: test_arg_i16:
; X32: # %bb.0:
-; X32-NEXT: movzwl 4(%esp), %eax
+; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
;
; X64-LABEL: test_arg_i16:
@@ -58,7 +58,7 @@ define i16 @test_arg_i16(i16 %a) {
define i32 @test_arg_i32(i32 %a) {
; X32-LABEL: test_arg_i32:
; X32: # %bb.0:
-; X32-NEXT: movl 4(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
;
; X64-LABEL: test_arg_i32:
@@ -71,8 +71,8 @@ define i32 @test_arg_i32(i32 %a) {
define i64 @test_arg_i64(i64 %a) {
; X32-LABEL: test_arg_i64:
; X32: # %bb.0:
-; X32-NEXT: movl 4(%esp), %eax
-; X32-NEXT: movl 8(%esp), %edx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: retl
;
; X64-LABEL: test_arg_i64:
@@ -85,13 +85,13 @@ define i64 @test_arg_i64(i64 %a) {
define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8) {
; X32-LABEL: test_i64_args_8:
; X32: # %bb.0:
-; X32-NEXT: movl 60(%esp), %eax
-; X32-NEXT: movl 64(%esp), %edx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: retl
;
; X64-LABEL: test_i64_args_8:
; X64: # %bb.0:
-; X64-NEXT: movq 16(%rsp), %rax
+; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: retq
ret i64 %arg8
}
@@ -114,7 +114,7 @@ define <8 x i32> @test_v8i32_args(<8 x i
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
-; X32-NEXT: movups 16(%esp), %xmm1
+; X32-NEXT: movups {{[0-9]+}}(%esp), %xmm1
; X32-NEXT: movaps %xmm2, %xmm0
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
@@ -154,10 +154,10 @@ define void @test_simple_arg_call(i32 %i
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
-; X32-NEXT: movl 16(%esp), %eax
-; X32-NEXT: movl 20(%esp), %ecx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, (%esp)
-; X32-NEXT: movl %eax, 4(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X32-NEXT: calll simple_arg_callee
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
@@ -182,15 +182,15 @@ define void @test_simple_arg8_call(i32 %
; X32: # %bb.0:
; X32-NEXT: subl $44, %esp
; X32-NEXT: .cfi_def_cfa_offset 48
-; X32-NEXT: movl 48(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %eax, (%esp)
-; X32-NEXT: movl %eax, 4(%esp)
-; X32-NEXT: movl %eax, 8(%esp)
-; X32-NEXT: movl %eax, 12(%esp)
-; X32-NEXT: movl %eax, 16(%esp)
-; X32-NEXT: movl %eax, 20(%esp)
-; X32-NEXT: movl %eax, 24(%esp)
-; X32-NEXT: movl %eax, 28(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X32-NEXT: calll simple_arg8_callee
; X32-NEXT: addl $44, %esp
; X32-NEXT: retl
@@ -200,7 +200,7 @@ define void @test_simple_arg8_call(i32 %
; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32
; X64-NEXT: movl %edi, (%rsp)
-; X64-NEXT: movl %edi, 8(%rsp)
+; X64-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; X64-NEXT: movl %edi, %esi
; X64-NEXT: movl %edi, %edx
; X64-NEXT: movl %edi, %ecx
@@ -247,12 +247,12 @@ define <8 x i32> @test_split_return_call
; X32-NEXT: subl $44, %esp
; X32-NEXT: .cfi_def_cfa_offset 48
; X32-NEXT: movaps %xmm0, (%esp) # 16-byte Spill
-; X32-NEXT: movaps %xmm1, 16(%esp) # 16-byte Spill
-; X32-NEXT: movdqu 48(%esp), %xmm1
+; X32-NEXT: movaps %xmm1, {{[0-9]+}}(%esp) # 16-byte Spill
+; X32-NEXT: movdqu {{[0-9]+}}(%esp), %xmm1
; X32-NEXT: movdqa %xmm2, %xmm0
; X32-NEXT: calll split_return_callee
; X32-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload
-; X32-NEXT: paddd 16(%esp), %xmm1 # 16-byte Folded Reload
+; X32-NEXT: paddd {{[0-9]+}}(%esp), %xmm1 # 16-byte Folded Reload
; X32-NEXT: addl $44, %esp
; X32-NEXT: retl
;
@@ -261,12 +261,12 @@ define <8 x i32> @test_split_return_call
; X64-NEXT: subq $40, %rsp
; X64-NEXT: .cfi_def_cfa_offset 48
; X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; X64-NEXT: movaps %xmm1, 16(%rsp) # 16-byte Spill
+; X64-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
; X64-NEXT: movdqa %xmm2, %xmm0
; X64-NEXT: movdqa %xmm3, %xmm1
; X64-NEXT: callq split_return_callee
; X64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload
-; X64-NEXT: paddd 16(%rsp), %xmm1 # 16-byte Folded Reload
+; X64-NEXT: paddd {{[0-9]+}}(%rsp), %xmm1 # 16-byte Folded Reload
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
%call = call <8 x i32> @split_return_callee(<8 x i32> %arg2)
@@ -279,7 +279,7 @@ define void @test_indirect_call(void()*
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
-; X32-NEXT: calll *16(%esp)
+; X32-NEXT: calll *{{[0-9]+}}(%esp)
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
;
@@ -306,7 +306,7 @@ define void @test_abi_exts_call(i8* %add
; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: .cfi_offset %esi, -12
; X32-NEXT: .cfi_offset %ebx, -8
-; X32-NEXT: movl 16(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movb (%eax), %bl
; X32-NEXT: movzbl %bl, %esi
; X32-NEXT: movl %esi, (%esp)
@@ -349,12 +349,12 @@ define void @test_variadic_call_1(i8** %
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
-; X32-NEXT: movl 16(%esp), %eax
-; X32-NEXT: movl 20(%esp), %ecx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl (%ecx), %ecx
; X32-NEXT: movl %eax, (%esp)
-; X32-NEXT: movl %ecx, 4(%esp)
+; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X32-NEXT: calll variadic_callee
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
@@ -381,15 +381,15 @@ define void @test_variadic_call_2(i8** %
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
-; X32-NEXT: movl 16(%esp), %eax
-; X32-NEXT: movl 20(%esp), %ecx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl (%ecx), %edx
; X32-NEXT: movl 4(%ecx), %ecx
; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: movl $4, %eax
; X32-NEXT: leal (%esp,%eax), %eax
-; X32-NEXT: movl %edx, 4(%esp)
+; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ecx, 4(%eax)
; X32-NEXT: calll variadic_callee
; X32-NEXT: addl $12, %esp
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir Tue Jan 23 08:08:15 2018
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
@@ -17,19 +18,10 @@
...
---
name: test_fadd_float
-# ALL-LABEL: name: test_fadd_float
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -38,27 +30,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr32 = COPY %xmm0
-# SSE-NEXT: %1:fr32 = COPY %xmm1
-# SSE-NEXT: %2:fr32 = ADDSSrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr32 = COPY %xmm0
-# AVX-NEXT: %1:fr32 = COPY %xmm1
-# AVX-NEXT: %2:fr32 = VADDSSrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr32x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr32x = VADDSSZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fadd_float
+ ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; SSE: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[ADDSSrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fadd_float
+ ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; AVX: [[VADDSSrr:%[0-9]+]]:fr32 = VADDSSrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VADDSSrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fadd_float
+ ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512F: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VADDSSZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fadd_float
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512VL: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VADDSSZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FADD %0, %1
@@ -68,19 +69,10 @@ body: |
...
---
name: test_fadd_double
-# ALL-LABEL: name: test_fadd_double
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -89,27 +81,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr64 = COPY %xmm0
-# SSE-NEXT: %1:fr64 = COPY %xmm1
-# SSE-NEXT: %2:fr64 = ADDSDrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr64 = COPY %xmm0
-# AVX-NEXT: %1:fr64 = COPY %xmm1
-# AVX-NEXT: %2:fr64 = VADDSDrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr64x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr64x = VADDSDZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fadd_double
+ ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; SSE: [[ADDSDrr:%[0-9]+]]:fr64 = ADDSDrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[ADDSDrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fadd_double
+ ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; AVX: [[VADDSDrr:%[0-9]+]]:fr64 = VADDSDrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VADDSDrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fadd_double
+ ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512F: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VADDSDZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fadd_double
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512VL: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VADDSDZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FADD %0, %1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir Tue Jan 23 08:08:15 2018
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
#RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK64 --check-prefix=CHECK_SMALL --check-prefix=CHECK_SMALL64 --check-prefix=CHECK_NOPIC64
#RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -code-model=large -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK64 --check-prefix=CHECK_LARGE --check-prefix=CHECK_LARGE64
#RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK32 --check-prefix=CHECK_SMALL --check-prefix=CHECK_SMALL32
@@ -16,29 +17,38 @@
}
---
name: test_float
-# CHECK64-LABEL: name: test_float
#
-# CHECK32-LABEL: name: test_float
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64: %0:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg
-# CHECK_SMALL64-NEXT: %xmm0 = COPY %0
-# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
-#
-# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT: %0:fr32 = MOVSSrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 32)
-# CHECK_LARGE64-NEXT: %xmm0 = COPY %0
-# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
-#
-# CHECK32: %0:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg
-# CHECK32-NEXT: %xmm0 = COPY %0
-# CHECK32-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1.entry:
+ ; CHECK_NOPIC64-LABEL: name: test_float
+ ; CHECK_NOPIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg
+ ; CHECK_NOPIC64: %xmm0 = COPY [[MOVSSrm]]
+ ; CHECK_NOPIC64: RET 0, implicit %xmm0
+ ; CHECK_LARGE64-LABEL: name: test_float
+ ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
+ ; CHECK_LARGE64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm [[MOV64ri]], 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 32)
+ ; CHECK_LARGE64: %xmm0 = COPY [[MOVSSrm]]
+ ; CHECK_LARGE64: RET 0, implicit %xmm0
+ ; CHECK_SMALL32-LABEL: name: test_float
+ ; CHECK_SMALL32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg
+ ; CHECK_SMALL32: %xmm0 = COPY [[MOVSSrm]]
+ ; CHECK_SMALL32: RET 0, implicit %xmm0
+ ; CHECK_LARGE32-LABEL: name: test_float
+ ; CHECK_LARGE32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg
+ ; CHECK_LARGE32: %xmm0 = COPY [[MOVSSrm]]
+ ; CHECK_LARGE32: RET 0, implicit %xmm0
+ ; CHECK_PIC64-LABEL: name: test_float
+ ; CHECK_PIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg
+ ; CHECK_PIC64: %xmm0 = COPY [[MOVSSrm]]
+ ; CHECK_PIC64: RET 0, implicit %xmm0
%0(s32) = G_FCONSTANT float 5.500000e+00
%xmm0 = COPY %0(s32)
RET 0, implicit %xmm0
@@ -46,38 +56,40 @@ body: |
...
---
name: test_double
-# CHECK64-LABEL: name: test_double
#
-# CHECK32-LABEL: name: test_double
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
-# CHECK_SMALL64: registers:
-# CHECK_SMALL64-NEXT: - { id: 0, class: fr64, preferred-register: '' }
#
-# CHECK_LARGE64: registers:
-# CHECK_LARGE64-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# CHECK_LARGE64-NEXT: - { id: 1, class: gr64, preferred-register: '' }
#
-# CHECK32: registers:
-# CHECK32-NEXT: - { id: 0, class: fr64, preferred-register: '' }
registers:
- { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64: %0:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg
-# CHECK_SMALL64-NEXT: %xmm0 = COPY %0
-# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
-#
-# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT: %0:fr64 = MOVSDrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 64)
-# CHECK_LARGE64-NEXT: %xmm0 = COPY %0
-# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
-#
-# CHECK32: %0:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg
-# CHECK32-NEXT: %xmm0 = COPY %0
-# CHECK32-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1.entry:
+ ; CHECK_NOPIC64-LABEL: name: test_double
+ ; CHECK_NOPIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg
+ ; CHECK_NOPIC64: %xmm0 = COPY [[MOVSDrm]]
+ ; CHECK_NOPIC64: RET 0, implicit %xmm0
+ ; CHECK_LARGE64-LABEL: name: test_double
+ ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
+ ; CHECK_LARGE64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm [[MOV64ri]], 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 64)
+ ; CHECK_LARGE64: %xmm0 = COPY [[MOVSDrm]]
+ ; CHECK_LARGE64: RET 0, implicit %xmm0
+ ; CHECK_SMALL32-LABEL: name: test_double
+ ; CHECK_SMALL32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg
+ ; CHECK_SMALL32: %xmm0 = COPY [[MOVSDrm]]
+ ; CHECK_SMALL32: RET 0, implicit %xmm0
+ ; CHECK_LARGE32-LABEL: name: test_double
+ ; CHECK_LARGE32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg
+ ; CHECK_LARGE32: %xmm0 = COPY [[MOVSDrm]]
+ ; CHECK_LARGE32: RET 0, implicit %xmm0
+ ; CHECK_PIC64-LABEL: name: test_double
+ ; CHECK_PIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg
+ ; CHECK_PIC64: %xmm0 = COPY [[MOVSDrm]]
+ ; CHECK_PIC64: RET 0, implicit %xmm0
%0(s64) = G_FCONSTANT double 5.500000e+00
%xmm0 = COPY %0(s64)
RET 0, implicit %xmm0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir Tue Jan 23 08:08:15 2018
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
@@ -17,19 +18,10 @@
...
---
name: test_fdiv_float
-# ALL-LABEL: name: test_fdiv_float
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -38,27 +30,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr32 = COPY %xmm0
-# SSE-NEXT: %1:fr32 = COPY %xmm1
-# SSE-NEXT: %2:fr32 = DIVSSrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr32 = COPY %xmm0
-# AVX-NEXT: %1:fr32 = COPY %xmm1
-# AVX-NEXT: %2:fr32 = VDIVSSrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr32x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr32x = VDIVSSZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fdiv_float
+ ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; SSE: [[DIVSSrr:%[0-9]+]]:fr32 = DIVSSrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[DIVSSrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fdiv_float
+ ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; AVX: [[VDIVSSrr:%[0-9]+]]:fr32 = VDIVSSrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VDIVSSrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fdiv_float
+ ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512F: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VDIVSSZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fdiv_float
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512VL: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VDIVSSZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FDIV %0, %1
@@ -68,19 +69,10 @@ body: |
...
---
name: test_fdiv_double
-# ALL-LABEL: name: test_fdiv_double
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -89,27 +81,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr64 = COPY %xmm0
-# SSE-NEXT: %1:fr64 = COPY %xmm1
-# SSE-NEXT: %2:fr64 = DIVSDrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr64 = COPY %xmm0
-# AVX-NEXT: %1:fr64 = COPY %xmm1
-# AVX-NEXT: %2:fr64 = VDIVSDrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr64x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr64x = VDIVSDZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fdiv_double
+ ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; SSE: [[DIVSDrr:%[0-9]+]]:fr64 = DIVSDrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[DIVSDrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fdiv_double
+ ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; AVX: [[VDIVSDrr:%[0-9]+]]:fr64 = VDIVSDrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VDIVSDrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fdiv_double
+ ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512F: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VDIVSDZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fdiv_double
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512VL: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VDIVSDZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FDIV %0, %1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir Tue Jan 23 08:08:15 2018
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
@@ -17,19 +18,10 @@
...
---
name: test_fmul_float
-# ALL-LABEL: name: test_fmul_float
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -38,27 +30,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr32 = COPY %xmm0
-# SSE-NEXT: %1:fr32 = COPY %xmm1
-# SSE-NEXT: %2:fr32 = MULSSrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr32 = COPY %xmm0
-# AVX-NEXT: %1:fr32 = COPY %xmm1
-# AVX-NEXT: %2:fr32 = VMULSSrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr32x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr32x = VMULSSZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fmul_float
+ ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[MULSSrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fmul_float
+ ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VMULSSrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fmul_float
+ ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VMULSSZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fmul_float
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VMULSSZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FMUL %0, %1
@@ -68,19 +69,10 @@ body: |
...
---
name: test_fmul_double
-# ALL-LABEL: name: test_fmul_double
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -89,27 +81,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr64 = COPY %xmm0
-# SSE-NEXT: %1:fr64 = COPY %xmm1
-# SSE-NEXT: %2:fr64 = MULSDrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr64 = COPY %xmm0
-# AVX-NEXT: %1:fr64 = COPY %xmm1
-# AVX-NEXT: %2:fr64 = VMULSDrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr64x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr64x = VMULSDZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fmul_double
+ ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[MULSDrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fmul_double
+ ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VMULSDrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fmul_double
+ ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VMULSDZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fmul_double
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VMULSDZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FMUL %0, %1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir?rev=323215&r1=323214&r2=323215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir Tue Jan 23 08:08:15 2018
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
@@ -17,19 +18,10 @@
...
---
name: test_fsub_float
-# ALL-LABEL: name: test_fsub_float
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -38,27 +30,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr32 = COPY %xmm0
-# SSE-NEXT: %1:fr32 = COPY %xmm1
-# SSE-NEXT: %2:fr32 = SUBSSrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr32 = COPY %xmm0
-# AVX-NEXT: %1:fr32 = COPY %xmm1
-# AVX-NEXT: %2:fr32 = VSUBSSrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr32x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr32x = VSUBSSZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fsub_float
+ ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; SSE: [[SUBSSrr:%[0-9]+]]:fr32 = SUBSSrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[SUBSSrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fsub_float
+ ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
+ ; AVX: [[VSUBSSrr:%[0-9]+]]:fr32 = VSUBSSrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VSUBSSrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fsub_float
+ ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512F: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VSUBSSZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fsub_float
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
+ ; AVX512VL: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VSUBSSZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FSUB %0, %1
@@ -68,19 +69,10 @@ body: |
...
---
name: test_fsub_double
-# ALL-LABEL: name: test_fsub_double
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+#
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
@@ -89,27 +81,36 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0:fr64 = COPY %xmm0
-# SSE-NEXT: %1:fr64 = COPY %xmm1
-# SSE-NEXT: %2:fr64 = SUBSDrr %0, %1
-# SSE-NEXT: %xmm0 = COPY %2
-# SSE-NEXT: RET 0, implicit %xmm0
-#
-# AVX: %0:fr64 = COPY %xmm0
-# AVX-NEXT: %1:fr64 = COPY %xmm1
-# AVX-NEXT: %2:fr64 = VSUBSDrr %0, %1
-# AVX-NEXT: %xmm0 = COPY %2
-# AVX-NEXT: RET 0, implicit %xmm0
-#
-# AVX512ALL: %0:fr64x = COPY %xmm0
-# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
-# AVX512ALL-NEXT: %2:fr64x = VSUBSDZrr %0, %1
-# AVX512ALL-NEXT: %xmm0 = COPY %2
-# AVX512ALL-NEXT: RET 0, implicit %xmm0
+#
+#
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; SSE-LABEL: name: test_fsub_double
+ ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; SSE: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[COPY]], [[COPY1]]
+ ; SSE: %xmm0 = COPY [[SUBSDrr]]
+ ; SSE: RET 0, implicit %xmm0
+ ; AVX-LABEL: name: test_fsub_double
+ ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
+ ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
+ ; AVX: [[VSUBSDrr:%[0-9]+]]:fr64 = VSUBSDrr [[COPY]], [[COPY1]]
+ ; AVX: %xmm0 = COPY [[VSUBSDrr]]
+ ; AVX: RET 0, implicit %xmm0
+ ; AVX512F-LABEL: name: test_fsub_double
+ ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512F: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY]], [[COPY1]]
+ ; AVX512F: %xmm0 = COPY [[VSUBSDZrr]]
+ ; AVX512F: RET 0, implicit %xmm0
+ ; AVX512VL-LABEL: name: test_fsub_double
+ ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
+ ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
+ ; AVX512VL: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY]], [[COPY1]]
+ ; AVX512VL: %xmm0 = COPY [[VSUBSDZrr]]
+ ; AVX512VL: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FSUB %0, %1
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