[llvm] r323202 - AArch64: get type from correct result when forming BFI/BFM

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Tue Jan 23 06:37:03 2018
New Revision: 323202

URL: http://llvm.org/viewvc/llvm-project?rev=323202&view=rev
Log:
AArch64: get type from correct result when forming BFI/BFM

Some nodes produce multiple values so when obtaining the type of an ISD::OR we
need to make sure we ask for the correct one.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=323202&r1=323201&r2=323202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Tue Jan 23 06:37:03 2018
@@ -2301,7 +2301,7 @@ static bool tryBitfieldInsertOpFromOr(SD
       continue;
 
     // Check the second part of the pattern
-    EVT VT = OrOpd1->getValueType(0);
+    EVT VT = OrOpd1Val.getValueType();
     assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
 
     // Compute the Known Zero for the candidate of the first operand.

Modified: llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll?rev=323202&r1=323201&r2=323202&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll Tue Jan 23 06:37:03 2018
@@ -480,3 +480,20 @@ define i32 @test9(i64 %b, i32 %e) {
   %h = or i32 %g, %f
   ret i32 %h
 }
+
+; CHECK-LABEL: test_complex_type:
+; CHECK: ldr d0, [x0], #8
+; CHECK: orr [[BOTH:x[0-9]+]], x0, x1, lsl #32
+; CHECK: str [[BOTH]], [x2]
+define <2 x i32> @test_complex_type(<2 x i32>* %addr, i64 %in, i64* %bf ) {
+  %vec = load <2 x i32>, <2 x i32>* %addr
+
+  %vec.next = getelementptr <2 x i32>, <2 x i32>* %addr, i32 1
+  %lo = ptrtoint <2 x i32>* %vec.next to i64
+
+  %hi = shl i64 %in, 32
+  %both = or i64 %lo, %hi
+  store i64 %both, i64* %bf
+
+  ret <2 x i32> %vec
+}