[PATCH] D42402: [GISel]: Eliminate redundant copies b/w VRegs of same regclass at the end of InstructionSelection

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar created this revision.
aditya_nandakumar added reviewers: qcolombet, dsanders, aemerson, rovka.
Herald added a subscriber: javed.absar.

A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up so that later passes don't have to all check to walk through the source of copies.


Repository:
  rL LLVM

https://reviews.llvm.org/D42402

Files:
  lib/CodeGen/GlobalISel/InstructionSelect.cpp
  test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
  test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
  test/CodeGen/AArch64/GlobalISel/select-br.mir
  test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
  test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
  test/CodeGen/AArch64/GlobalISel/select-store.mir
  test/CodeGen/AArch64/GlobalISel/select-trunc.mir
  test/CodeGen/AArch64/GlobalISel/select.mir
  test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
  test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
  test/CodeGen/X86/GlobalISel/select-ext.mir
  test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
  test/CodeGen/X86/GlobalISel/select-merge-vec512.mir

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