[PATCH] D42401: [ARM] Expand long shifts for Thumb1 to __aeabi_ calls
Weiming Zhao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 22 17:11:49 PST 2018
weimingz created this revision.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar, aemerson.
For long shifts, the inlined version takes about 20 instructions on Thumb1. To avoid the code bloat, expand to __aeabi_ calls if target is Thumb1.
Repository:
rL LLVM
https://reviews.llvm.org/D42401
Files:
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/shift-i64.ll
Index: test/CodeGen/ARM/shift-i64.ll
===================================================================
--- test/CodeGen/ARM/shift-i64.ll
+++ test/CodeGen/ARM/shift-i64.ll
@@ -1,7 +1,9 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix=EXPAND
define i64 @test_shl(i64 %val, i64 %amt) {
; CHECK-LABEL: test_shl:
+; EXPAND-LABEL: test_shl:
; First calculate the hi part when the shift amount is small enough that it
; contains components from both halves. It'll be returned in r1 so that's a
; reasonable place for it to end up.
@@ -22,29 +24,34 @@
; CHECK: lsl r0, r0, r2
; CHECK: movge r0, #0
+; EXPAND: bl __aeabi_llsl
%res = shl i64 %val, %amt
ret i64 %res
}
; Explanation for lshr is pretty much the reverse of shl.
define i64 @test_lshr(i64 %val, i64 %amt) {
; CHECK-LABEL: test_lshr:
+; EXPAND-LABEL: test_lshr:
; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
; CHECK: lsr r0, r0, r2
; CHECK: orr r0, r0, r1, lsl [[REVERSE_SHIFT]]
; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
; CHECK: cmp [[EXTRA_SHIFT]], #0
; CHECK: lsrge r0, r1, [[EXTRA_SHIFT]]
; CHECK: lsr r1, r1, r2
; CHECK: movge r1, #0
+
+; EXPAND: bl __aeabi_llsr
%res = lshr i64 %val, %amt
ret i64 %res
}
; One minor difference for ashr: the high bits must be "hi >> 31" if the shift
; amount is large to get the right sign bit.
define i64 @test_ashr(i64 %val, i64 %amt) {
; CHECK-LABEL: test_ashr:
+; EXPAND-LABEL: test_ashr:
; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
; CHECK: asr [[HI_TMP:.*]], r1, r2
; CHECK: lsr r0, r0, r2
@@ -54,6 +61,8 @@
; CHECK: asrge [[HI_TMP]], r1, #31
; CHECK: asrge r0, r1, [[EXTRA_SHIFT]]
; CHECK: mov r1, [[HI_TMP]]
+
+; EXPAND: bl __aeabi_lasr
%res = ashr i64 %val, %amt
ret i64 %res
}
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -820,6 +820,13 @@
setOperationAction(ISD::SRA, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
+ // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
+ if (Subtarget->isThumb1Only()) {
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ }
+
setOperationAction(ISD::ADDC, MVT::i32, Custom);
setOperationAction(ISD::ADDE, MVT::i32, Custom);
setOperationAction(ISD::SUBC, MVT::i32, Custom);
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