[PATCH] D29935: [RISCV 13/n] Codegen for conditional branches

[Sameer AbuAsal via Phabricator via llvm-commits]

sabuasal added inline comments.
Herald added subscribers: niosHD, simoncook, johnrusso, rbar.


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Comment at: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td:70
 // A 13-bit signed immediate where the least significant bit is zero.
-def simm13_lsb0 : Operand<XLenVT> {
+def simm13_lsb0 : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
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Hi Alex, 

I have two questions about this:
1)  Why don't we have this type inherting from ImmLeaf?
2) Why is this not using XLenVT?

I am trying to add ImmLeaf since I need them for some checks for that type but it is causing a crash while running table gen about some type compatibility ("Type set is empty for each HW mode")


Repository:
  rL LLVM

https://reviews.llvm.org/D29935