[llvm] r322997 - [X86] Autogenerate complete checks on a couple tests. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 19 14:04:20 PST 2018
Author: ctopper
Date: Fri Jan 19 14:04:20 2018
New Revision: 322997
URL: http://llvm.org/viewvc/llvm-project?rev=322997&view=rev
Log:
[X86] Autogenerate complete checks on a couple tests. NFC
Modified:
llvm/trunk/test/CodeGen/X86/bswap.ll
llvm/trunk/test/CodeGen/X86/pr12360.ll
Modified: llvm/trunk/test/CodeGen/X86/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bswap.ll?rev=322997&r1=322996&r2=322997&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bswap.ll Fri Jan 19 14:04:20 2018
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; bswap should be constant folded when it is passed a constant argument
; RUN: llc < %s -mtriple=i686-- -mcpu=i686 | FileCheck %s
@@ -11,45 +12,71 @@ declare i64 @llvm.bswap.i64(i64)
define i16 @W(i16 %A) {
; CHECK-LABEL: W:
-; CHECK: rolw $8, %ax
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: rolw $8, %ax
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: W:
-; CHECK64: rolw $8, %
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: rolw $8, %di
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
%Z = call i16 @llvm.bswap.i16( i16 %A ) ; <i16> [#uses=1]
ret i16 %Z
}
define i32 @X(i32 %A) {
; CHECK-LABEL: X:
-; CHECK: bswapl %eax
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: X:
-; CHECK64: bswapl %
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: bswapl %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
%Z = call i32 @llvm.bswap.i32( i32 %A ) ; <i32> [#uses=1]
ret i32 %Z
}
define i64 @Y(i64 %A) {
; CHECK-LABEL: Y:
-; CHECK: bswapl %eax
-; CHECK: bswapl %edx
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: bswapl %edx
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: Y:
-; CHECK64: bswapq %
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: bswapq %rdi
+; CHECK64-NEXT: movq %rdi, %rax
+; CHECK64-NEXT: retq
%Z = call i64 @llvm.bswap.i64( i64 %A ) ; <i64> [#uses=1]
ret i64 %Z
}
; rdar://9164521
define i32 @test1(i32 %a) nounwind readnone {
-entry:
; CHECK-LABEL: test1:
-; CHECK: bswapl [[REG:%.*]]
-; CHECK: shrl $16, [[REG]]
-
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: shrl $16, %eax
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: test1:
-; CHECK64: bswapl [[REG:%.*]]
-; CHECK64: shrl $16, [[REG]]
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: bswapl %edi
+; CHECK64-NEXT: shrl $16, %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+entry:
+
%and = lshr i32 %a, 8
%shr3 = and i32 %and, 255
%and2 = shl i32 %a, 8
@@ -59,14 +86,21 @@ entry:
}
define i32 @test2(i32 %a) nounwind readnone {
-entry:
; CHECK-LABEL: test2:
-; CHECK: bswapl [[REG:%.*]]
-; CHECK: sarl $16, [[REG]]
-
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: sarl $16, %eax
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: test2:
-; CHECK64: bswapl [[REG:%.*]]
-; CHECK64: sarl $16, [[REG]]
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: bswapl %edi
+; CHECK64-NEXT: sarl $16, %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+entry:
+
%and = lshr i32 %a, 8
%shr4 = and i32 %and, 255
%and2 = shl i32 %a, 8
@@ -85,12 +119,23 @@ entry:
; rdar://problem/14814049
define i64 @not_bswap() {
; CHECK-LABEL: not_bswap:
-; CHECK-NOT: bswapl
-; CHECK: ret
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzwl var16, %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: shrl $8, %ecx
+; CHECK-NEXT: shll $8, %eax
+; CHECK-NEXT: orl %ecx, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: not_bswap:
-; CHECK64-NOT: bswapq
-; CHECK64: ret
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK64-NEXT: movq %rax, %rcx
+; CHECK64-NEXT: shrq $8, %rcx
+; CHECK64-NEXT: shlq $8, %rax
+; CHECK64-NEXT: orq %rcx, %rax
+; CHECK64-NEXT: retq
%init = load i16, i16* @var16
%big = zext i16 %init to i64
@@ -108,13 +153,17 @@ define i64 @not_bswap() {
define i64 @not_useful_bswap() {
; CHECK-LABEL: not_useful_bswap:
-; CHECK-NOT: bswapl
-; CHECK: ret
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl var8, %eax
+; CHECK-NEXT: shll $8, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: not_useful_bswap:
-; CHECK64-NOT: bswapq
-; CHECK64: ret
-
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movzbl {{.*}}(%rip), %eax
+; CHECK64-NEXT: shlq $8, %rax
+; CHECK64-NEXT: retq
%init = load i8, i8* @var8
%big = zext i8 %init to i64
@@ -131,15 +180,19 @@ define i64 @not_useful_bswap() {
define i64 @finally_useful_bswap() {
; CHECK-LABEL: finally_useful_bswap:
-; CHECK: bswapl [[REG:%.*]]
-; CHECK: shrl $16, [[REG]]
-; CHECK: ret
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzwl var16, %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: shrl $16, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retl
+;
; CHECK64-LABEL: finally_useful_bswap:
-; CHECK64: bswapq [[REG:%.*]]
-; CHECK64: shrq $48, [[REG]]
-; CHECK64: ret
-
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK64-NEXT: bswapq %rax
+; CHECK64-NEXT: shrq $48, %rax
+; CHECK64-NEXT: retq
%init = load i16, i16* @var16
%big = zext i16 %init to i64
Modified: llvm/trunk/test/CodeGen/X86/pr12360.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr12360.ll?rev=322997&r1=322996&r2=322997&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr12360.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr12360.ll Fri Jan 19 14:04:20 2018
@@ -1,9 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define zeroext i1 @f1(i8* %x) {
; CHECK-LABEL: f1:
-; CHECK: movb (%rdi), %al
-; CHECK-NEXT: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movb (%rdi), %al
+; CHECK-NEXT: retq
entry:
%0 = load i8, i8* %x, align 1, !range !0
@@ -13,8 +15,9 @@ entry:
define zeroext i1 @f2(i8* %x) {
; CHECK-LABEL: f2:
-; CHECK: movb (%rdi), %al
-; CHECK-NEXT: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movb (%rdi), %al
+; CHECK-NEXT: retq
entry:
%0 = load i8, i8* %x, align 1, !range !0
@@ -28,6 +31,10 @@ entry:
; check that we don't build a "trunc" from i1 to i1, which would assert.
define zeroext i1 @f3(i1 %x) {
; CHECK-LABEL: f3:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
entry:
%tobool = icmp ne i1 %x, 0
@@ -37,7 +44,11 @@ entry:
; check that we don't build a trunc when other bits are needed
define zeroext i1 @f4(i32 %x) {
; CHECK-LABEL: f4:
-; CHECK: and
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: shrl $15, %edi
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
entry:
%y = and i32 %x, 32768
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