[llvm] r322925 - Move tests to the correct place
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 22:08:16 PST 2018
Author: matze
Date: Thu Jan 18 22:08:15 2018
New Revision: 322925
URL: http://llvm.org/viewvc/llvm-project?rev=322925&view=rev
Log:
Move tests to the correct place
test/CodeGen/MIR is for testing the MIR parser/printer. Tests for passes
and targets belong to test/CodeGen/TARGETNAME.
Added:
llvm/trunk/test/CodeGen/AArch64/spill-fold.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir
llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
llvm/trunk/test/CodeGen/AMDGPU/fold-multiple.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir
llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir
llvm/trunk/test/CodeGen/X86/dynamic-regmask.ll
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll
llvm/trunk/test/CodeGen/X86/opt_phis.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir
llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir
llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir
llvm/trunk/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
- copied, changed from r322924, llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
Removed:
llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir
llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll
llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir
llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir
llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir
llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
Copied: llvm/trunk/test/CodeGen/AArch64/spill-fold.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/spill-fold.mir?p2=llvm/trunk/test/CodeGen/AArch64/spill-fold.mir&p1=llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/fold-multiple.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fold-multiple.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/fold-multiple.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (from r322924, llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir&p1=llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir?p2=llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir (from r322924, llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir?p2=llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir&p1=llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/spill-fold.mir (removed)
@@ -1,82 +0,0 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass greedy -verify-machineinstrs -o - %s | FileCheck %s
---- |
- define i64 @test_subreg_spill_fold() { ret i64 0 }
- define i64 @test_subreg_spill_fold2() { ret i64 0 }
- define i64 @test_subreg_spill_fold3() { ret i64 0 }
- define i64 @test_subreg_fill_fold() { ret i64 0 }
- define double @test_subreg_fill_fold2() { ret double 0.0 }
-...
----
-# CHECK-LABEL: name: test_subreg_spill_fold
-# Ensure that the spilled subreg COPY is eliminated and folded into the spill store.
-name: test_subreg_spill_fold
-registers:
- - { id: 0, class: gpr64 }
-body: |
- bb.0:
- ; CHECK: STRXui %xzr, %stack.0, 0 :: (store 8 into %stack.0)
- undef %0.sub_32 = COPY %wzr
- INLINEASM &nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
- %x0 = COPY %0
- RET_ReallyLR implicit %x0
-...
----
-# CHECK-LABEL: name: test_subreg_spill_fold2
-# Similar to test_subreg_spill_fold, but with a %0 register class not containing %WZR.
-name: test_subreg_spill_fold2
-registers:
- - { id: 0, class: gpr64sp }
-body: |
- bb.0:
- ; CHECK: STRXui %xzr, %stack.0, 0 :: (store 8 into %stack.0)
- undef %0.sub_32 = COPY %wzr
- INLINEASM &nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
- %x0 = ADDXri %0, 1, 0
- RET_ReallyLR implicit %x0
-...
----
-# CHECK-LABEL: name: test_subreg_spill_fold3
-# Similar to test_subreg_spill_fold, but with a cross register class copy.
-name: test_subreg_spill_fold3
-registers:
- - { id: 0, class: fpr64 }
-body: |
- bb.0:
- ; CHECK: STRXui %xzr, %stack.0, 0 :: (store 8 into %stack.0)
- undef %0.ssub = COPY %wzr
- INLINEASM &nop, 1, 12, implicit-def dead %d0, 12, implicit-def dead %d1, 12, implicit-def dead %d2, 12, implicit-def dead %d3, 12, implicit-def dead %d4, 12, implicit-def dead %d5, 12, implicit-def dead %d6, 12, implicit-def dead %d7, 12, implicit-def dead %d8, 12, implicit-def dead %d9, 12, implicit-def dead %d10, 12, implicit-def dead %d11, 12, implicit-def dead %d12, 12, implicit-def dead %d13, 12, implicit-def dead %d14, 12, implicit-def dead %d15, 12, implicit-def dead %d16, 12, implicit-def dead %d17, 12, implicit-def dead %d18, 12, implicit-def dead %d19, 12, implicit-def dead %d20, 12, implicit-def dead %d21, 12, implicit-def dead %d22, 12, implicit-def dead %d23, 12, implicit-def dead %d24, 12, implicit-def dead %d25, 12, implicit-def dead %d26, 12, implicit-def dead %d27, 12, implicit-def dead %d28, 12, implicit-def dead %d29, 12, implicit-def dead %d30, 12, implicit-def %d31
- %x0 = COPY %0
- RET_ReallyLR implicit %x0
-...
----
-# CHECK-LABEL: name: test_subreg_fill_fold
-# Ensure that the filled COPY is eliminated and folded into the fill load.
-name: test_subreg_fill_fold
-registers:
- - { id: 0, class: gpr32 }
- - { id: 1, class: gpr64 }
-body: |
- bb.0:
- %0 = COPY %wzr
- INLINEASM &nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
- ; CHECK: undef %1.sub_32:gpr64 = LDRWui %stack.0, 0 :: (load 4 from %stack.0)
- undef %1.sub_32 = COPY %0
- %x0 = COPY %1
- RET_ReallyLR implicit %x0
-...
----
-# CHECK-LABEL: name: test_subreg_fill_fold2
-# Similar to test_subreg_fill_fold, but with a cross-class copy.
-name: test_subreg_fill_fold2
-registers:
- - { id: 0, class: gpr32 }
- - { id: 1, class: fpr64 }
-body: |
- bb.0:
- %0 = COPY %wzr
- INLINEASM &nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
- ; CHECK: undef %1.ssub:fpr64 = LDRSui %stack.0, 0 :: (load 4 from %stack.0)
- undef %1.ssub = COPY %0
- %d0 = COPY %1
- RET_ReallyLR implicit %d0
-...
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir (removed)
@@ -1,709 +0,0 @@
-# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
---- |
- define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f32.add = fadd float %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile float %f32.add, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f32_1.0_multi_f16_use() #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f32.add = fadd float %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile float %f32.add, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f32_1.0_one_f32_use_one_f16_use () #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f32.add = fadd float %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile float %f32.add, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f32_1.0_one_f32_use_multi_f16_use () #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f16.add1 = fadd half %f16.val1, 0xH3C00
- %f32.add = fadd float %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile half %f16.add1, half addrspace(1)* undef
- store volatile float %f32.add, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_i32_1_multi_f16_use() #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH0001
- %f16.add1 = fadd half %f16.val1, 0xH0001
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile half %f16.add1,half addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_i32_m2_one_f32_use_multi_f16_use () #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xHFFFE
- %f16.add1 = fadd half %f16.val1, 0xHFFFE
- %f32.add = fadd float %f32.val, 0xffffffffc0000000
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile half %f16.add1, half addrspace(1)* undef
- store volatile float %f32.add, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f16_1.0_multi_f32_use() #0 {
- %f32.val0 = load volatile float, float addrspace(1)* undef
- %f32.val1 = load volatile float, float addrspace(1)* undef
- %f32.val = load volatile float, float addrspace(1)* undef
- %f32.add0 = fadd float %f32.val0, 1.0
- %f32.add1 = fadd float %f32.val1, 1.0
- store volatile float %f32.add0, float addrspace(1)* undef
- store volatile float %f32.add1, float addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f16_1.0_other_high_bits_multi_f16_use() #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile half, half addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f32.add = fadd half %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile half %f32.add, half addrspace(1)* undef
- ret void
- }
-
- define amdgpu_kernel void @add_f16_1.0_other_high_bits_use_f16_f32() #0 {
- %f16.val0 = load volatile half, half addrspace(1)* undef
- %f16.val1 = load volatile half, half addrspace(1)* undef
- %f32.val = load volatile half, half addrspace(1)* undef
- %f16.add0 = fadd half %f16.val0, 0xH3C00
- %f32.add = fadd half %f32.val, 1.000000e+00
- store volatile half %f16.add0, half addrspace(1)* undef
- store volatile half %f32.add, half addrspace(1)* undef
- ret void
- }
-
- attributes #0 = { nounwind }
-
-...
----
-
-# f32 1.0 with a single use should be folded as the low 32-bits of a
-# literal constant.
-
-# CHECK-LABEL: name: add_f32_1.0_one_f16_use
-# CHECK: %13:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit %exec
-
-name: add_f32_1.0_one_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = V_MOV_B32_e32 1065353216, implicit %exec
- %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-# Materialized f32 inline immediate should not be folded into the f16
-# operands
-
-# CHECK-LABEL: name: add_f32_1.0_multi_f16_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %14:vgpr_32 = V_ADD_F16_e32 killed %11, %13, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 killed %12, killed %13, implicit %exec
-
-
-name: add_f32_1.0_multi_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %13 = V_MOV_B32_e32 1065353216, implicit %exec
- %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec
- %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# f32 1.0 should be folded into the single f32 use as an inline
-# immediate, and folded into the single f16 use as a literal constant
-
-# CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit %exec
-# CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
-
-name: add_f32_1.0_one_f32_use_one_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
- - { id: 16, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %14 = V_MOV_B32_e32 1065353216, implicit %exec
- %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
- %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# f32 1.0 should be folded for the single f32 use as an inline
-# constant, and not folded as a multi-use literal for the f16 cases
-
-# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
-# CHECK: %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %11, %14, implicit %exec
-# CHECK: %16:vgpr_32 = V_ADD_F16_e32 %12, %14, implicit %exec
-# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
-
-name: add_f32_1.0_one_f32_use_multi_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
- - { id: 16, class: vgpr_32 }
- - { id: 17, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %14 = V_MOV_B32_e32 1065353216, implicit %exec
- %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
- %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec
- %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-# CHECK-LABEL: name: add_i32_1_multi_f16_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit %exec
-# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit %exec
-
-
-name: add_i32_1_multi_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %13 = V_MOV_B32_e32 1, implicit %exec
- %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec
- %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
-# CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit %exec
-# CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit %exec
-# CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit %exec
-
-name: add_i32_m2_one_f32_use_multi_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
- - { id: 16, class: vgpr_32 }
- - { id: 17, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %14 = V_MOV_B32_e32 -2, implicit %exec
- %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
- %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec
- %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# f32 1.0 should be folded for the single f32 use as an inline
-# constant, and not folded as a multi-use literal for the f16 cases
-
-# CHECK-LABEL: name: add_f16_1.0_multi_f32_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 15360, implicit %exec
-# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit %exec
-
-name: add_f16_1.0_multi_f32_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %13 = V_MOV_B32_e32 15360, implicit %exec
- %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec
- %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# The low 16-bits are an inline immediate, but the high bits are junk
-# FIXME: Should be able to fold this
-
-# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 80886784, implicit %exec
-# CHECK: %14:vgpr_32 = V_ADD_F16_e32 %11, %13, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit %exec
-
-name: add_f16_1.0_other_high_bits_multi_f16_use
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %13 = V_MOV_B32_e32 80886784, implicit %exec
- %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit %exec
- %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec
- BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- S_ENDPGM
-
-...
----
-
-# FIXME: Should fold inline immediate into f16 and literal use into
-# f32 instruction.
-
-# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 305413120, implicit %exec
-# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit %exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit %exec
-name: add_f16_1.0_other_high_bits_use_f16_f32
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: sgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_32 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_32 }
- - { id: 8, class: sreg_32 }
- - { id: 9, class: sreg_32 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: vgpr_32 }
- - { id: 12, class: vgpr_32 }
- - { id: 13, class: vgpr_32 }
- - { id: 14, class: vgpr_32 }
- - { id: 15, class: vgpr_32 }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- %4 = IMPLICIT_DEF
- %5 = COPY %4.sub1
- %6 = IMPLICIT_DEF
- %7 = COPY %6.sub0
- %8 = S_MOV_B32 61440
- %9 = S_MOV_B32 -1
- %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
- %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
- %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
- %13 = V_MOV_B32_e32 305413120, implicit %exec
- %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec
- %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
- BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
- S_ENDPGM
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/fold-multiple.mir (removed)
@@ -1,40 +0,0 @@
-# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
---- |
- define amdgpu_kernel void @test() #0 {
- ret void
- }
-
- attributes #0 = { nounwind }
-
-...
----
-
-# This used to crash / trigger an assertion, because re-scanning the use list
-# after constant-folding the definition of %3 lead to the definition of %2
-# being processed twice.
-
-# CHECK-LABEL: name: test
-# CHECK: %2:vgpr_32 = V_LSHLREV_B32_e32 2, killed %0, implicit %exec
-# CHECK: %4:vgpr_32 = V_AND_B32_e32 8, killed %2, implicit %exec
-
-name: test
-tracksRegLiveness: true
-registers:
- - { id: 0, class: vgpr_32 }
- - { id: 1, class: sreg_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_32 }
- - { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_128 }
-body: |
- bb.0 (%ir-block.0):
- %0 = IMPLICIT_DEF
- %1 = S_MOV_B32 2
- %2 = V_LSHLREV_B32_e64 %1, killed %0, implicit %exec
- %3 = S_LSHL_B32 %1, killed %1, implicit-def dead %scc
- %4 = V_AND_B32_e64 killed %2, killed %3, implicit %exec
- %5 = IMPLICIT_DEF
- BUFFER_STORE_DWORD_OFFSET killed %4, killed %5, 0, 0, 0, 0, 0, implicit %exec
- S_ENDPGM
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir (removed)
@@ -1,122 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
-
---- |
- ; ModuleID = '<stdin>'
- source_filename = "<stdin>"
- target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-
- ; Function Attrs: nounwind readnone
- declare i32 @llvm.amdgcn.workitem.id.x() #0
-
- ; Function Attrs: nounwind
- define amdgpu_kernel void @atomic_max_i32_noret(
- i32 addrspace(1)* %out,
- i32 addrspace(1)* addrspace(1)* %in,
- i32 addrspace(1)* %x,
- i32 %y) #1 {
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idxprom = sext i32 %tid to i64
- %tid.gep = getelementptr i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %in, i64 %idxprom
- %ptr = load volatile i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %tid.gep
- %xor = xor i32 %tid, 1
- %cmp = icmp ne i32 %xor, 0
- %1 = call { i1, i64 } @llvm.amdgcn.if(i1 %cmp)
- %2 = extractvalue { i1, i64 } %1, 0
- %3 = extractvalue { i1, i64 } %1, 1
- br i1 %2, label %atomic, label %exit
-
- atomic: ; preds = %0
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 100
- %ret = atomicrmw max i32 addrspace(1)* %gep, i32 %y seq_cst
- br label %exit
-
- exit: ; preds = %atomic, %0
- call void @llvm.amdgcn.end.cf(i64 %3)
- ret void
- }
-
- declare { i1, i64 } @llvm.amdgcn.if(i1)
-
- declare void @llvm.amdgcn.end.cf(i64)
-
- ; Function Attrs: nounwind
- declare void @llvm.stackprotector(i8*, i8**) #3
-
- attributes #0 = { nounwind readnone "target-cpu"="tahiti" }
- attributes #1 = { nounwind "target-cpu"="tahiti" }
- attributes #2 = { readnone }
- attributes #3 = { nounwind }
-
-...
----
-
-# CHECK-LABEL: name: atomic_max_i32_noret
-
-# CHECK-LABEL: bb.1.atomic:
-# CHECK: BUFFER_ATOMIC_SMAX_ADDR64
-# CHECK-NEXT: S_WAITCNT 3952
-# CHECK-NEXT: BUFFER_WBINVL1_VOL
-
-name: atomic_max_i32_noret
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
- - { reg: '%sgpr0_sgpr1' }
- - { reg: '%vgpr0' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0 (%ir-block.0):
- successors: %bb.1.atomic(0x40000000), %bb.2.exit(0x40000000)
- liveins: %vgpr0, %sgpr0_sgpr1
-
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %vgpr1 = V_ASHRREV_I32_e32 31, %vgpr0, implicit %exec
- %vgpr1_vgpr2 = V_LSHL_B64 %vgpr0_vgpr1, 3, implicit %exec
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 0
- S_WAITCNT 127
- %vgpr1_vgpr2 = BUFFER_LOAD_DWORDX2_ADDR64 killed %vgpr1_vgpr2, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 8 from %ir.tid.gep)
- %vgpr0 = V_XOR_B32_e32 1, killed %vgpr0, implicit %exec
- V_CMP_NE_U32_e32 0, killed %vgpr0, implicit-def %vcc, implicit %exec
- %sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 killed %vcc, implicit-def %exec, implicit-def %scc, implicit %exec
- %sgpr2_sgpr3 = S_XOR_B64 %exec, killed %sgpr2_sgpr3, implicit-def dead %scc
- SI_MASK_BRANCH %bb.2.exit, implicit %exec
-
- bb.1.atomic:
- successors: %bb.2.exit(0x80000000)
- liveins: %sgpr4_sgpr5_sgpr6_sgpr7:0x0000000C, %sgpr0_sgpr1, %sgpr2_sgpr3, %vgpr1_vgpr2_vgpr3_vgpr4:0x00000003
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 15, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- dead %vgpr0 = V_MOV_B32_e32 -1, implicit %exec
- dead %vgpr0 = V_MOV_B32_e32 61440, implicit %exec
- %sgpr4_sgpr5 = S_MOV_B64 0
- S_WAITCNT 127
- %vgpr0 = V_MOV_B32_e32 killed %sgpr0, implicit %exec, implicit %exec
- S_WAITCNT 3952
- BUFFER_ATOMIC_SMAX_ADDR64 killed %vgpr0, killed %vgpr1_vgpr2, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 400, 0, implicit %exec :: (volatile load seq_cst 4 from %ir.gep)
-
- bb.2.exit:
- liveins: %sgpr2_sgpr3
-
- %exec = S_OR_B64 %exec, killed %sgpr2_sgpr3, implicit-def %scc
- S_ENDPGM
-
-...
-
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir (removed)
@@ -1,163 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
-
---- |
- ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
- source_filename = "memory-legalizer-multiple-mem-operands.ll"
- target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-
- define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
- entry:
- %scratch0 = alloca [8192 x i32]
- %scratch1 = alloca [8192 x i32]
- %scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32*
- store i32 1, i32* %scratchptr01
- %scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32*
- store i32 2, i32* %scratchptr12
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
-
- if: ; preds = %entry
- %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
- %if_value = load atomic i32, i32* %if_ptr syncscope("workgroup") seq_cst, align 4
- br label %done, !structurizecfg.uniform !0
-
- else: ; preds = %entry
- %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
- %else_value = load atomic i32, i32* %else_ptr syncscope("agent") unordered, align 4
- br label %done, !structurizecfg.uniform !0
-
- done: ; preds = %else, %if
- %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
- store i32 %value, i32 addrspace(1)* %out
- ret void
- }
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.if(i1) #1
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.else(i64) #1
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.break(i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.if.break(i1, i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.else.break(i64, i64) #2
-
- ; Function Attrs: convergent nounwind
- declare i1 @llvm.amdgcn.loop(i64) #1
-
- ; Function Attrs: convergent nounwind
- declare void @llvm.amdgcn.end.cf(i64) #1
-
- attributes #0 = { "target-cpu"="gfx803" }
- attributes #1 = { convergent nounwind }
- attributes #2 = { convergent nounwind readnone }
-
- !0 = !{}
-
-...
----
-
-# CHECK-LABEL: name: multiple_mem_operands
-
-# CHECK-LABEL: bb.3.done:
-# CHECK: S_WAITCNT 3952
-# CHECK-NEXT: BUFFER_LOAD_DWORD_OFFEN
-# CHECK-NEXT: S_WAITCNT 3952
-# CHECK-NEXT: BUFFER_WBINVL1_VOL
-
-name: multiple_mem_operands
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
-liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '' }
- - { reg: '%sgpr3', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 65540
- offsetAdjustment: 0
- maxAlignment: 4
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- savePoint: ''
- restorePoint: ''
-fixedStack:
- - { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
- isImmutable: false, isAliased: false, callee-saved-register: '' }
-stack:
- - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
- stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
- di-expression: '', di-location: '' }
- - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
- alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
- di-variable: '', di-expression: '', di-location: '' }
-constants:
-body: |
- bb.0.entry:
- successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
- liveins: %sgpr0_sgpr1, %sgpr3
-
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- %sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr10 = S_MOV_B32 4294967295, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr11 = S_MOV_B32 15204352, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %vgpr0 = V_MOV_B32_e32 1, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr01)
- S_WAITCNT 127
- S_CMP_LG_U32 killed %sgpr2, 0, implicit-def %scc
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 2, implicit %exec
- %vgpr1 = V_MOV_B32_e32 32772, implicit %exec
- BUFFER_STORE_DWORD_OFFEN killed %vgpr0, killed %vgpr1, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr12)
- S_CBRANCH_SCC0 %bb.1.if, implicit killed %scc
-
- bb.2.else:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 32772, implicit %exec
- S_BRANCH %bb.3.done
-
- bb.1.if:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 4, implicit %exec
-
- bb.3.done:
- liveins: %sgpr3, %sgpr4_sgpr5, %sgpr8_sgpr9_sgpr10_sgpr11, %vgpr0, %sgpr0
-
- S_WAITCNT 127
- %sgpr0 = S_LSHL_B32 killed %sgpr0, 2, implicit-def dead %scc
- %vgpr0 = V_ADD_I32_e32 killed %sgpr0, killed %vgpr0, implicit-def dead %vcc, implicit %exec
- %vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed %vgpr0, killed %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (load syncscope("agent") unordered 4 from %ir.else_ptr), (load syncscope("workgroup") seq_cst 4 from %ir.if_ptr)
- %vgpr1 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr1_vgpr2, implicit %sgpr4_sgpr5
- %vgpr2 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit %sgpr4_sgpr5, implicit %exec
- S_WAITCNT 3952
- FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.out)
- S_ENDPGM
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (removed)
@@ -1,161 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
-
---- |
- ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
- source_filename = "memory-legalizer-multiple-mem-operands.ll"
- target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-
- define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
- entry:
- %scratch0 = alloca [8192 x i32]
- %scratch1 = alloca [8192 x i32]
- %scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32*
- store i32 1, i32* %scratchptr01
- %scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32*
- store i32 2, i32* %scratchptr12
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
-
- if: ; preds = %entry
- %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
- %if_value = load i32, i32* %if_ptr, align 4, !nontemporal !1
- br label %done, !structurizecfg.uniform !0
-
- else: ; preds = %entry
- %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
- %else_value = load i32, i32* %else_ptr, align 4, !nontemporal !1
- br label %done, !structurizecfg.uniform !0
-
- done: ; preds = %else, %if
- %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
- store i32 %value, i32 addrspace(1)* %out
- ret void
- }
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.if(i1) #1
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.else(i64) #1
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.break(i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.if.break(i1, i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.else.break(i64, i64) #2
-
- ; Function Attrs: convergent nounwind
- declare i1 @llvm.amdgcn.loop(i64) #1
-
- ; Function Attrs: convergent nounwind
- declare void @llvm.amdgcn.end.cf(i64) #1
-
- attributes #0 = { "target-cpu"="gfx803" }
- attributes #1 = { convergent nounwind }
- attributes #2 = { convergent nounwind readnone }
-
- !0 = !{}
- !1 = !{i32 1}
-
-...
----
-
-# CHECK-LABEL: name: multiple_mem_operands
-
-# CHECK-LABEL: bb.3.done:
-# CHECK: BUFFER_LOAD_DWORD_OFFEN killed %vgpr0, killed %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 1, 1, 0
-
-name: multiple_mem_operands
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
-liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '' }
- - { reg: '%sgpr3', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 65540
- offsetAdjustment: 0
- maxAlignment: 4
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- savePoint: ''
- restorePoint: ''
-fixedStack:
- - { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
- isImmutable: false, isAliased: false, callee-saved-register: '' }
-stack:
- - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
- stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
- di-expression: '', di-location: '' }
- - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
- alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
- di-variable: '', di-expression: '', di-location: '' }
-constants:
-body: |
- bb.0.entry:
- successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
- liveins: %sgpr0_sgpr1, %sgpr3
-
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- %sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr10 = S_MOV_B32 4294967295, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr11 = S_MOV_B32 15204352, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %vgpr0 = V_MOV_B32_e32 1, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr01)
- S_WAITCNT 127
- S_CMP_LG_U32 killed %sgpr2, 0, implicit-def %scc
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 2, implicit %exec
- %vgpr1 = V_MOV_B32_e32 32772, implicit %exec
- BUFFER_STORE_DWORD_OFFEN killed %vgpr0, killed %vgpr1, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr12)
- S_CBRANCH_SCC0 %bb.1.if, implicit killed %scc
-
- bb.2.else:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 32772, implicit %exec
- S_BRANCH %bb.3.done
-
- bb.1.if:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 4, implicit %exec
-
- bb.3.done:
- liveins: %sgpr3, %sgpr4_sgpr5, %sgpr8_sgpr9_sgpr10_sgpr11, %vgpr0, %sgpr0
-
- S_WAITCNT 127
- %sgpr0 = S_LSHL_B32 killed %sgpr0, 2, implicit-def dead %scc
- %vgpr0 = V_ADD_I32_e32 killed %sgpr0, killed %vgpr0, implicit-def dead %vcc, implicit %exec
- %vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed %vgpr0, killed %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (non-temporal load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
- %vgpr1 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr1_vgpr2, implicit %sgpr4_sgpr5
- %vgpr2 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit %sgpr4_sgpr5, implicit %exec
- S_WAITCNT 3952
- FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.out)
- S_ENDPGM
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (removed)
@@ -1,161 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
-
---- |
- ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
- source_filename = "memory-legalizer-multiple-mem-operands.ll"
- target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-
- define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
- entry:
- %scratch0 = alloca [8192 x i32]
- %scratch1 = alloca [8192 x i32]
- %scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32*
- store i32 1, i32* %scratchptr01
- %scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32*
- store i32 2, i32* %scratchptr12
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
-
- if: ; preds = %entry
- %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
- %if_value = load i32, i32* %if_ptr, align 4, !nontemporal !1
- br label %done, !structurizecfg.uniform !0
-
- else: ; preds = %entry
- %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
- %else_value = load i32, i32* %else_ptr, align 4
- br label %done, !structurizecfg.uniform !0
-
- done: ; preds = %else, %if
- %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
- store i32 %value, i32 addrspace(1)* %out
- ret void
- }
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.if(i1) #1
-
- ; Function Attrs: convergent nounwind
- declare { i1, i64 } @llvm.amdgcn.else(i64) #1
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.break(i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.if.break(i1, i64) #2
-
- ; Function Attrs: convergent nounwind readnone
- declare i64 @llvm.amdgcn.else.break(i64, i64) #2
-
- ; Function Attrs: convergent nounwind
- declare i1 @llvm.amdgcn.loop(i64) #1
-
- ; Function Attrs: convergent nounwind
- declare void @llvm.amdgcn.end.cf(i64) #1
-
- attributes #0 = { "target-cpu"="gfx803" }
- attributes #1 = { convergent nounwind }
- attributes #2 = { convergent nounwind readnone }
-
- !0 = !{}
- !1 = !{i32 1}
-
-...
----
-
-# CHECK-LABEL: name: multiple_mem_operands
-
-# CHECK-LABEL: bb.3.done:
-# CHECK: BUFFER_LOAD_DWORD_OFFEN killed %vgpr0, killed %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0
-
-name: multiple_mem_operands
-alignment: 0
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
-liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '' }
- - { reg: '%sgpr3', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 65540
- offsetAdjustment: 0
- maxAlignment: 4
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- savePoint: ''
- restorePoint: ''
-fixedStack:
- - { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
- isImmutable: false, isAliased: false, callee-saved-register: '' }
-stack:
- - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
- stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
- di-expression: '', di-location: '' }
- - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
- alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
- di-variable: '', di-expression: '', di-location: '' }
-constants:
-body: |
- bb.0.entry:
- successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
- liveins: %sgpr0_sgpr1, %sgpr3
-
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- %sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr10 = S_MOV_B32 4294967295, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %sgpr11 = S_MOV_B32 15204352, implicit-def %sgpr8_sgpr9_sgpr10_sgpr11
- %vgpr0 = V_MOV_B32_e32 1, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr01)
- S_WAITCNT 127
- S_CMP_LG_U32 killed %sgpr2, 0, implicit-def %scc
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 2, implicit %exec
- %vgpr1 = V_MOV_B32_e32 32772, implicit %exec
- BUFFER_STORE_DWORD_OFFEN killed %vgpr0, killed %vgpr1, %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.scratchptr12)
- S_CBRANCH_SCC0 %bb.1.if, implicit killed %scc
-
- bb.2.else:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 32772, implicit %exec
- S_BRANCH %bb.3.done
-
- bb.1.if:
- successors: %bb.3.done(0x80000000)
- liveins: %sgpr0_sgpr1, %sgpr4_sgpr5, %sgpr3, %sgpr8_sgpr9_sgpr10_sgpr11
-
- %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- S_WAITCNT 3855
- %vgpr0 = V_MOV_B32_e32 4, implicit %exec
-
- bb.3.done:
- liveins: %sgpr3, %sgpr4_sgpr5, %sgpr8_sgpr9_sgpr10_sgpr11, %vgpr0, %sgpr0
-
- S_WAITCNT 127
- %sgpr0 = S_LSHL_B32 killed %sgpr0, 2, implicit-def dead %scc
- %vgpr0 = V_ADD_I32_e32 killed %sgpr0, killed %vgpr0, implicit-def dead %vcc, implicit %exec
- %vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed %vgpr0, killed %sgpr8_sgpr9_sgpr10_sgpr11, %sgpr3, 0, 0, 0, 0, implicit %exec :: (load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
- %vgpr1 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr1_vgpr2, implicit %sgpr4_sgpr5
- %vgpr2 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit %sgpr4_sgpr5, implicit %exec
- S_WAITCNT 3952
- FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.out)
- S_ENDPGM
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir (removed)
@@ -1,23 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
----
-name: foo
-body: |
- bb.0:
- B %bb.2
-
- bb.1:
- BX_RET 14, 0
-
- bb.2:
- Bcc %bb.1, 1, %cpsr
-
- bb.3:
- B %bb.1
-...
-
-# We should get a single block containing the BX_RET, with no successors at all
-
-# CHECK: body:
-# CHECK-NEXT: bb.0:
-# CHECK-NEXT: BX_RET
-
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir (removed)
@@ -1,65 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -o - %s -run-pass if-converter | FileCheck %s
----
-name: f1
-body: |
- bb.0:
- successors: %bb.1
-
- B %bb.1
-
- bb.1:
- successors: %bb.2, %bb.4
-
- Bcc %bb.4, 1, %cpsr
-
- bb.2:
- successors: %bb.3, %bb.5
-
- Bcc %bb.5, 1, %cpsr
-
- bb.3:
- successors: %bb.5
-
- B %bb.5
-
- bb.4:
- successors:
-
- bb.5:
- successors: %bb.1, %bb.6
-
- Bcc %bb.1, 1, %cpsr
-
- bb.6:
- BX_RET 14, _
-
-...
-
-# IfConversion.cpp/canFallThroughTo thought there was a fallthrough from
-# bb.4 to bb5 even if the successor list was empty.
-# bb.4 is empty, so it surely looks like it can fallthrough, but this is what
-# happens for a bb just containing an "unreachable".
-
-#CHECK: body: |
-#CHECK: bb.0:
-#CHECK: successors: %bb.1
-
-#CHECK: bb.1:
-#CHECK: successors: %bb.3({{.*}}), %bb.2
-
-# The original brr_cond from bb.1, jumping to the empty bb
-#CHECK: Bcc %bb.2
-#CHECK: B %bb.3
-
-# Empty bb.2, originally containing "unreachable" and thus has no successors
-# and we cannot guess them: we should print an empty list of successors.
-#CHECK: bb.2:
-#CHECK: successors:{{ *$}}
-
-#CHECK: bb.3:
-#CHECK: successors: %bb.1
-
-# Conditional BX_RET and then loop back to bb.1
-#CHECK: BX_RET 0
-#CHECK: B %bb.1
-
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir (removed)
@@ -1,30 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
----
-name: foo
-body: |
- bb.0:
- Bcc %bb.2, 1, %cpsr
-
- bb.1:
- %sp = tADDspi %sp, 1, 14, _
- B %bb.3
-
- bb.2:
- %sp = tADDspi %sp, 2, 14, _
- B %bb.3
-
- bb.3:
- successors:
- %sp = tADDspi %sp, 3, 14, _
- BX_RET 14, _
-...
-
-# Diamond testcase with unanalyzable instruction in the BB following the
-# diamond.
-
-# CHECK: body: |
-# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir (removed)
@@ -1,48 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
----
-name: foo
-body: |
- bb.0:
- Bcc %bb.2, 1, %cpsr
-
- bb.1:
- successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 1, 14, _
- Bcc %bb.3, 1, %cpsr
- B %bb.4
-
- bb.2:
- successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 2, 14, _
- Bcc %bb.3, 1, %cpsr
- B %bb.4
-
- bb.3:
- successors:
- %sp = tADDspi %sp, 3, 14, _
- BX_RET 14, _
-
- bb.4:
- successors:
- %sp = tADDspi %sp, 4, 14, _
- BX_RET 14, _
-...
-
-# Forked-diamond testcase with unanalyzable instructions in both the True and
-# False BBs following the forked diamond.
-
-# CHECK: body: |
-# CHECK: bb.0:
-# CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
-
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: Bcc %bb.2, 1, %cpsr
-
-# CHECK: bb.1:
-# CHECK: %sp = tADDspi %sp, 4, 14, %noreg
-# CHECK: BX_RET 14, %noreg
-
-# CHECK: bb.2:
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir (removed)
@@ -1,33 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
----
-name: f1
-body: |
- bb.0:
-
- bb.1:
- Bcc %bb.3, 0, %cpsr
-
- bb.2:
-
- bb.3:
- Bcc %bb.1, 0, %cpsr
-
- bb.4:
- successors: %bb.1
- tBRIND %r1, 14, _
-...
-
-# We should only get bb.1 as successor to bb.1. No zero percent probability
-# edge from bb.1 to bb.2. There shouldn't even be a bb.2 at all.
-
-# CHECK: body: |
-# CHECK: bb.0:
-# CHECK: successors: %bb.1(0x80000000)
-
-# CHECK: bb.1:
-# CHECK: successors: %bb.1(0x80000000)
-# CHECK-NOT: %bb.2(0x00000000)
-# CHECK: tBRIND %r1, 1, %cpsr
-# CHECK: B %bb.1
-
-#CHECK-NOT: bb.2:
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir (removed)
@@ -1,25 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
----
-name: foo
-body: |
- bb.0:
- Bcc %bb.2, 0, %cpsr
-
- bb.1:
- successors:
- BX_RET 14, _
-
- bb.2:
- successors:
- %sp = tADDspi %sp, 2, 14, _
- BX_RET 14, _
-...
-
-# Simple testcase with unanalyzable instructions in both TBB and FBB.
-
-# CHECK: body: |
-# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 0, %cpsr
-# CHECK: BX_RET 0, %cpsr
-# CHECK: BX_RET 14, %noreg
-
Removed: llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir (removed)
@@ -1,52 +0,0 @@
-# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
---- |
- declare void @__stack_chk_fail()
- declare void @bar()
-
- define void @foo() {
- ret void
- }
-...
----
-name: foo
-body: |
-
- bb.0:
- Bcc %bb.1, 1, %cpsr
- B %bb.2
-
- bb.1:
- Bcc %bb.3, 0, %cpsr
-
- bb.2:
- successors:
- tBL 14, %cpsr, @__stack_chk_fail
-
- bb.3:
- successors:
- %sp = tADDspi %sp, 2, 14, _
- %sp = tADDspi %sp, 2, 14, _
- tTAILJMPdND @bar, 14, %cpsr
-...
-
-# bb.2 has no successors, presumably because __stack_chk_fail doesn't return,
-# so there should be no edge from bb.2 to bb.3.
-# Nevertheless, IfConversion treats bb.1, bb.2, bb.3 as a triangle and
-# inserts a predicated copy of bb.2 in bb.1.
-
-# This caused r302876 to die with a failed assertion.
-
-# CHECK: bb.0:
-# CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
-# CHECK: Bcc %bb.2, 1, %cpsr
-
-# CHECK: bb.1:
-# CHECK-NOT: successors: %bb
-# CHECK: tBL 14, %cpsr, @__stack_chk_fail
-
-# CHECK: bb.2:
-# CHECK-NOT: successors: %bb
-# CHECK: tBL 1, %cpsr, @__stack_chk_fail
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: tTAILJMPdND @bar, 14, %cpsr
Removed: llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
-; RUN: FileCheck %s < %t.mir
-; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
-; Check that callee saved registers are printed in a format that can then be parsed.
-
-declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
-
-define i32 @caller(i32 %a0) nounwind {
- %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
- %b2 = add i32 %b1, %a0
- ret i32 %b2
-}
-; CHECK: name: caller
-; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w)
-; CHECK: RET 0, %eax
-
-define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
- %b1 = mul i32 7, %e0
- %b2 = udiv i32 5, %e0
- %b3 = mul i32 7, %d0
- %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
- %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
- %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
- ret {i32, i32, i32} %b6
-}
-; CHECK: name: test_callee
-; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',
-; CHECK: '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',
-; CHECK: '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]
-; CHECK: RET 0, %eax, %ecx, %edx
Removed: llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir (removed)
@@ -1,37 +0,0 @@
-# RUN: llc -run-pass opt-phis -march=x86-64 -o - %s | FileCheck %s
---- |
- define void @test() {
- ret void
- }
-
- !llvm.dbg.cu = !{!1}
- !llvm.module.flags = !{!2, !3}
- !llvm.ident = !{!4}
-
- !0 = !DIFile(filename: "foo.c", directory: "/bar")
- !1 = distinct !DICompileUnit(language: DW_LANG_C, file: !0, producer: "My Compiler")
- !2 = !{i32 2, !"Dwarf Version", i32 4}
- !3 = !{i32 2, !"Debug Info Version", i32 3}
- !4 = !{!"My Compiler"}
- !5 = distinct !DISubprogram(name: "test")
- !6 = !DILocation(line: 7, column: 11, scope: !5)
- !7 = !DILocalVariable(name: "l", scope: !5)
-
-...
----
-name: test
-tracksRegLiveness: true
-body: |
- bb.0:
- %0:gr32 = IMPLICIT_DEF
-
- bb.1:
- %1:gr32 = PHI %0, %bb.0, %2, %bb.1
- DBG_VALUE debug-use %1, debug-use _, !7, !DIExpression(), debug-location !6
- %2:gr32 = IMPLICIT_DEF
- JMP_1 %bb.1
-...
-
-# The PHI should be removed since it's only used in a DBG_VALUE
-# CHECK-LABEL: bb.1:
-# CHECK-NOT: PHI
Removed: llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir (removed)
@@ -1,182 +0,0 @@
-# RUN: llc -o - %s -run-pass=shrink-wrap | FileCheck %s
---- |
- ; ModuleID = '<stdin>'
- source_filename = "t.c"
- target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
- target triple = "i386-pc-windows-msvc19.11.25508"
-
- ; Function Attrs: nounwind
- define x86_fastcallcc i32 @"@shrink_wrap_basic at 16"(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) local_unnamed_addr #0 !dbg !8 {
- entry:
- %c.addr = alloca i32, align 4
- tail call void @llvm.dbg.value(metadata i32 %d, metadata !13, metadata !DIExpression()), !dbg !19
- tail call void @llvm.dbg.value(metadata i32 %c, metadata !14, metadata !DIExpression()), !dbg !20
- store i32 %c, i32* %c.addr, align 4, !tbaa !21
- tail call void @llvm.dbg.value(metadata i32 %b, metadata !15, metadata !DIExpression()), !dbg !25
- tail call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !26
- %cmp = icmp slt i32 %a, %b, !dbg !27
- br i1 %cmp, label %return, label %for.cond.preheader, !dbg !29
-
- for.cond.preheader: ; preds = %entry
- %0 = add i32 %c, -1, !dbg !30
- br label %for.cond, !dbg !30
-
- for.cond: ; preds = %for.cond, %for.cond.preheader
- %lsr.iv = phi i32 [ %lsr.iv.next, %for.cond ], [ %0, %for.cond.preheader ]
- call void @llvm.dbg.value(metadata i32 undef, metadata !17, metadata !DIExpression()), !dbg !32
- call void @llvm.dbg.value(metadata i32* %c.addr, metadata !14, metadata !DIExpression()), !dbg !20
- %call = call i32 @doSomething(i32* nonnull %c.addr) #3, !dbg !33
- call void @llvm.dbg.value(metadata !2, metadata !17, metadata !DIExpression()), !dbg !32
- %lsr.iv.next = add i32 %lsr.iv, 1, !dbg !30
- %cmp1 = icmp slt i32 %lsr.iv.next, %d, !dbg !30
- br i1 %cmp1, label %for.cond, label %return, !dbg !34, !llvm.loop !35
-
- return: ; preds = %for.cond, %entry
- %retval.0 = phi i32 [ %a, %entry ], [ %call, %for.cond ]
- ret i32 %retval.0, !dbg !37
- }
-
- declare i32 @doSomething(i32*) local_unnamed_addr
-
- ; Function Attrs: nounwind readnone speculatable
- declare void @llvm.dbg.value(metadata, metadata, metadata) #2
-
- ; Function Attrs: nounwind
- declare void @llvm.stackprotector(i8*, i8**) #3
-
- attributes #0 = { nounwind }
- attributes #2 = { nounwind readnone speculatable }
- attributes #3 = { nounwind }
-
- !llvm.dbg.cu = !{!0}
- !llvm.module.flags = !{!3, !4, !5, !6}
- !llvm.ident = !{!7}
-
- !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
- !1 = !DIFile(filename: "t.c", directory: "C:\5Csrc\5Cllvm-project\5Cbuild", checksumkind: CSK_MD5, checksum: "32f118fd5dd7e65ff7733c49b2f804ef")
- !2 = !{}
- !3 = !{i32 1, !"NumRegisterParameters", i32 0}
- !4 = !{i32 2, !"CodeView", i32 1}
- !5 = !{i32 2, !"Debug Info Version", i32 3}
- !6 = !{i32 1, !"wchar_size", i32 2}
- !7 = !{!"clang version 6.0.0 "}
- !8 = distinct !DISubprogram(name: "shrink_wrap_basic", linkageName: "\01 at shrink_wrap_basic@16", scope: !1, file: !1, line: 2, type: !9, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !12)
- !9 = !DISubroutineType(cc: DW_CC_BORLAND_msfastcall, types: !10)
- !10 = !{!11, !11, !11, !11, !11}
- !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
- !12 = !{!13, !14, !15, !16, !17}
- !13 = !DILocalVariable(name: "d", arg: 4, scope: !8, file: !1, line: 2, type: !11)
- !14 = !DILocalVariable(name: "c", arg: 3, scope: !8, file: !1, line: 2, type: !11)
- !15 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 2, type: !11)
- !16 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)
- !17 = !DILocalVariable(name: "i", scope: !18, file: !1, line: 5, type: !11)
- !18 = distinct !DILexicalBlock(scope: !8, file: !1, line: 5, column: 3)
- !19 = !DILocation(line: 2, column: 59, scope: !8)
- !20 = !DILocation(line: 2, column: 52, scope: !8)
- !21 = !{!22, !22, i64 0}
- !22 = !{!"int", !23, i64 0}
- !23 = !{!"omnipotent char", !24, i64 0}
- !24 = !{!"Simple C/C++ TBAA"}
- !25 = !DILocation(line: 2, column: 45, scope: !8)
- !26 = !DILocation(line: 2, column: 38, scope: !8)
- !27 = !DILocation(line: 3, column: 9, scope: !28)
- !28 = distinct !DILexicalBlock(scope: !8, file: !1, line: 3, column: 7)
- !29 = !DILocation(line: 3, column: 7, scope: !8)
- !30 = !DILocation(line: 5, column: 21, scope: !31)
- !31 = distinct !DILexicalBlock(scope: !18, file: !1, line: 5, column: 3)
- !32 = !DILocation(line: 5, column: 12, scope: !18)
- !33 = !DILocation(line: 0, scope: !8)
- !34 = !DILocation(line: 5, column: 3, scope: !18)
- !35 = distinct !{!35, !34, !36}
- !36 = !DILocation(line: 6, column: 19, scope: !18)
- !37 = !DILocation(line: 8, column: 1, scope: !8)
-
-...
----
-name: '@shrink_wrap_basic at 16'
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
-liveins:
- - { reg: '%ecx', virtual-reg: '' }
- - { reg: '%edx', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 4
- adjustsStack: false
- hasCalls: true
- stackProtector: ''
- maxCallFrameSize: 4294967295
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- # CHECK: savePoint: '%bb.1'
- # CHECK: restorePoint: '%bb.3'
- savePoint: ''
- restorePoint: ''
-fixedStack:
- - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
- isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
- - { id: 1, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
- isImmutable: false, isAliased: false, callee-saved-register: '',
- callee-saved-restored: true }
-stack:
-constants:
-body: |
- bb.0.entry:
- successors: %bb.4(0x40000000), %bb.1(0x40000000)
- liveins: %ecx, %edx
-
- DBG_VALUE debug-use %edx, debug-use %noreg, !15, !DIExpression(), debug-location !25
- DBG_VALUE debug-use %ecx, debug-use %noreg, !16, !DIExpression(), debug-location !26
- %eax = COPY %ecx
- DBG_VALUE %fixed-stack.0, 0, !16, !DIExpression(), debug-location !26
- DBG_VALUE %fixed-stack.1, 0, !15, !DIExpression(), debug-location !25
- CMP32rr %eax, killed %edx, implicit-def %eflags, debug-location !27
- JL_1 %bb.4, implicit killed %eflags, debug-location !29
- JMP_1 %bb.1, debug-location !29
-
- bb.1.for.cond.preheader:
- successors: %bb.2(0x80000000)
-
- %esi = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (load 4 from %fixed-stack.0)
- DBG_VALUE debug-use %esi, debug-use %noreg, !13, !DIExpression(), debug-location !19
- %edi = MOV32rm %fixed-stack.1, 1, %noreg, 0, %noreg :: (load 4 from %fixed-stack.1)
- DBG_VALUE debug-use %edi, debug-use %noreg, !14, !DIExpression(), debug-location !20
- %edi = DEC32r killed %edi, implicit-def dead %eflags, debug-location !30
- %ebx = LEA32r %fixed-stack.1, 1, %noreg, 0, %noreg
-
- bb.2.for.cond:
- successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- liveins: %ebx, %edi, %esi
-
- ADJCALLSTACKDOWN32 4, 0, 4, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp, debug-location !33
- DBG_VALUE %fixed-stack.1, 0, !14, !DIExpression(), debug-location !20
- PUSH32r %ebx, implicit-def %esp, implicit %esp, debug-location !33
- CFI_INSTRUCTION adjust_cfa_offset 4, debug-location !33
- CALLpcrel32 @doSomething, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp, implicit-def %eax, debug-location !33
- ADJCALLSTACKUP32 4, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp, debug-location !33
- %edi = INC32r killed %edi, implicit-def dead %eflags, debug-location !30
- CMP32rr %edi, %esi, implicit-def %eflags, debug-location !30
- JL_1 %bb.2, implicit killed %eflags, debug-location !34
-
- bb.3:
- successors: %bb.4(0x80000000)
- liveins: %eax
-
-
- bb.4.return:
- liveins: %eax
-
- RET 8, %eax, debug-location !37
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir (removed)
@@ -1,30 +0,0 @@
-# RUN: llc -mtriple=x86_64-- %s -o - -run-pass=simple-register-coalescing | FileCheck %s
----
-name: f
-body: |
- bb.0:
- JB_1 %bb.2, undef implicit killed %eflags
- JMP_1 %bb.1
-
- bb.1:
- %0 : gr64 = IMPLICIT_DEF
- NOOP implicit-def undef %1.sub_32bit : gr64
- NOOP implicit-def %1.sub_16bit : gr64
- JMP_1 %bb.3
-
- bb.2:
- NOOP implicit-def %0
- %1 = COPY %0
-
- bb.3:
- NOOP implicit killed %0
- NOOP implicit killed %1
-...
-
-# We should have a setting of both sub_32bit and sub_16bit. The first one
-# should be undef and not dead, and the second should not be undef.
-
-# CHECK-NOT: dead
-# CHECK: NOOP implicit-def undef %1.sub_32bit
-# CHECK-NOT: undef
-# CHECK-NEXT: NOOP implicit-def %1.sub_16bit
Removed: llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir?rev=322924&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir (removed)
@@ -1,38 +0,0 @@
-# RUN: llc -march=x86-64 %s -o - -run-pass=processimpdefs -run-pass=unreachable-mbb-elimination | FileCheck %s
----
-name: f
-tracksRegLiveness: true
-registers:
- - { id: 0, class: gr32, preferred-register: '' }
- - { id: 1, class: gr32, preferred-register: '' }
- - { id: 2, class: gr32, preferred-register: '' }
-body: |
- bb.0:
- %0 = IMPLICIT_DEF
- JMP_1 %bb.1
-
- bb.1:
- %1 = PHI %0, %bb.0, %2, %bb.2
- %2 = ADD32ri8 killed %1, 1, implicit-def %eflags
- JMP_1 %bb.3
-
- bb.2:
- JMP_1 %bb.1
-
- bb.3:
-...
-
-# bb2 above is dead and should be removed and the PHI should be replaced with a
-# COPY from an undef value since the bb0 value in the PHI is undef.
-
-# CHECK: bb.0:
-# CHECK: successors: %bb.1
-# CHECK: JMP_1 %bb.1
-
-# CHECK: bb.1:
-# CHECK: successors: %bb.2
-# CHECK: [[TMP1:%[0-9]+]]:gr32 = COPY undef %{{[0-9]+}}
-# CHECK: %{{[0-9]+}}:gr32 = ADD32ri8 killed [[TMP1]], 1
-# CHECK: JMP_1 %bb.2
-
-# CHECK: bb.2:
Copied: llvm/trunk/test/CodeGen/X86/dynamic-regmask.ll (from r322924, llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dynamic-regmask.ll?p2=llvm/trunk/test/CodeGen/X86/dynamic-regmask.ll&p1=llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/opt_phis.mir (from r322924, llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/opt_phis.mir?p2=llvm/trunk/test/CodeGen/X86/opt_phis.mir&p1=llvm/trunk/test/CodeGen/MIR/X86/opt_phis.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir (from r322924, llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir?p2=llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir&p1=llvm/trunk/test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir (from r322924, llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir?p2=llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir&p1=llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/unreachable-mbb-undef-phi.mir (from r322924, llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unreachable-mbb-undef-phi.mir?p2=llvm/trunk/test/CodeGen/X86/unreachable-mbb-undef-phi.mir&p1=llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir&r1=322924&r2=322925&rev=322925&view=diff
==============================================================================
(empty)
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