[llvm] r322910 - [X86] Add intrinsic support for the RDPID instruction
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 15:52:31 PST 2018
Author: ctopper
Date: Thu Jan 18 15:52:31 2018
New Revision: 322910
URL: http://llvm.org/viewvc/llvm-project?rev=322910&view=rev
Log:
[X86] Add intrinsic support for the RDPID instruction
This adds a new instrinsic to support the rdpid instruction. The implementation is a bit weird because the intrinsic is defined as always returning 32-bits, but the assembler support thinks the instruction produces a 64-bit register in 64-bit mode. But really it zeros the upper 32 bits. So I had to add separate patterns where 64-bit mode uses an extract_subreg.
Differential Revision: https://reviews.llvm.org/D42205
Added:
llvm/trunk/test/CodeGen/X86/rdpid.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu Jan 18 15:52:31 2018
@@ -63,6 +63,12 @@ let TargetPrefix = "x86" in {
Intrinsic<[llvm_i64_ty], [llvm_i32_ty], []>;
}
+// Read processor ID.
+let TargetPrefix = "x86" in {
+ def int_x86_rdpid : GCCBuiltin<"__builtin_ia32_rdpid">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+}
+
//===----------------------------------------------------------------------===//
// CET SS
let TargetPrefix = "x86" in {
Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Thu Jan 18 15:52:31 2018
@@ -1255,7 +1255,9 @@ bool sys::getHostCPUFeatures(StringMap<b
Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
- Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
+ Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
+
+ Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
bool HasLeafD = MaxLevel >= 0xd &&
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Thu Jan 18 15:52:31 2018
@@ -249,6 +249,8 @@ def FeatureCLFLUSHOPT : SubtargetFeature
"Flush A Cache Line Optimized">;
def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
"Cache Line Write Back">;
+def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
+ "Support RDPID instructions">;
// On some processors, instructions that implicitly take two memory operands are
// slow. In practice, this means that CALL, PUSH, and POP with memory operands
// should be avoided in favor of a MOV + register CALL/PUSH/POP.
@@ -752,7 +754,8 @@ def ICLFeatures : ProcessorFeatures<CNLF
FeatureVPCLMULQDQ,
FeatureVPOPCNTDQ,
FeatureGFNI,
- FeatureCLWB
+ FeatureCLWB,
+ FeatureRDPID
]>;
class IcelakeProc<string Name> : ProcModel<Name, SkylakeServerModel,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jan 18 15:52:31 2018
@@ -878,6 +878,7 @@ def HasSHSTK : Predicate<"Subtarget-
def HasIBT : Predicate<"Subtarget->hasIBT()">;
def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
def HasCLWB : Predicate<"Subtarget->hasCLWB()">;
+def HasRDPID : Predicate<"Subtarget->hasRDPID()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Thu Jan 18 15:52:31 2018
@@ -700,14 +700,22 @@ let Uses = [RAX, RBX, RCX, RDX], Defs =
//===----------------------------------------------------------------------===//
// RDPID Instruction
let SchedRW = [WriteSystem] in {
-def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
- "rdpid\t$src", [], IIC_RDPID>, XS,
- Requires<[Not64BitMode]>;
-def RDPID64 : I<0xC7, MRM7r, (outs GR64:$src), (ins),
- "rdpid\t$src", [], IIC_RDPID>, XS,
- Requires<[In64BitMode]>;
+def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
+ "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))], IIC_RDPID>, XS,
+ Requires<[Not64BitMode, HasRDPID]>;
+def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins),
+ "rdpid\t$dst", [], IIC_RDPID>, XS,
+ Requires<[In64BitMode, HasRDPID]>;
} // SchedRW
+let Predicates = [In64BitMode, HasRDPID] in {
+ // Due to silly instruction definition, we have to compensate for the
+ // instruction outputing a 64-bit register.
+ def : Pat<(int_x86_rdpid),
+ (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
+}
+
+
//===----------------------------------------------------------------------===//
// PTWRITE Instruction
let SchedRW = [WriteSystem] in {
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jan 18 15:52:31 2018
@@ -315,6 +315,7 @@ void X86Subtarget::initializeEnvironment
HasSGX = false;
HasCLFLUSHOPT = false;
HasCLWB = false;
+ HasRDPID = false;
IsPMULLDSlow = false;
IsSHLDSlow = false;
IsUAMem16Slow = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=322910&r1=322909&r2=322910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Jan 18 15:52:31 2018
@@ -345,6 +345,9 @@ protected:
/// Processor supports Cache Line Write Back instruction
bool HasCLWB;
+ /// Processor support RDPID instruction
+ bool HasRDPID;
+
/// Use software floating point for code generation.
bool UseSoftFloat;
@@ -579,6 +582,7 @@ public:
bool hasIBT() const { return HasIBT; }
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
bool hasCLWB() const { return HasCLWB; }
+ bool hasRDPID() const { return HasRDPID; }
bool isXRaySupported() const override { return is64Bit(); }
Added: llvm/trunk/test/CodeGen/X86/rdpid.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rdpid.ll?rev=322910&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rdpid.ll (added)
+++ llvm/trunk/test/CodeGen/X86/rdpid.ll Thu Jan 18 15:52:31 2018
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=rdpid | FileCheck %s --check-prefix=CHECK --check-prefix=X86-64
+; RUN: llc < %s -mtriple=i686-- -mattr=rdpid | FileCheck %s --check-prefix=CHECK --check-prefix=X86
+
+define i32 @test_builtin_rdpid() {
+; X86-64-LABEL: test_builtin_rdpid:
+; X86-64: # %bb.0:
+; X86-64-NEXT: rdpid %rax
+; X86-64-NEXT: # kill: def %eax killed %eax killed %rax
+; X86-64-NEXT: retq
+;
+; X86-LABEL: test_builtin_rdpid:
+; X86: # %bb.0:
+; X86-NEXT: rdpid %eax
+; X86-NEXT: retl
+ %1 = tail call i32 @llvm.x86.rdpid()
+ ret i32 %1
+}
+
+declare i32 @llvm.x86.rdpid()
+
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