[PATCH] D42097: [SelectionDAG] Convert assert to condtion
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Thu Jan 18 01:23:54 PST 2018
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This revision was automatically updated to reflect the committed changes.
Closed by commit rL322823: [SelectionDAG] Convert assert to condtion (authored by sam_parker, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D42097?vs=129930&id=130368#toc
Repository:
rL LLVM
https://reviews.llvm.org/D42097
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -171,10 +171,9 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
SDValue Op = N->getOperand(0);
if (Op.getValueType().isVector()
- && Op.getValueType().getVectorNumElements() == 1) {
- assert(!isSimpleLegalType(Op.getValueType()));
+ && Op.getValueType().getVectorNumElements() == 1
+ && !isSimpleLegalType(Op.getValueType()))
Op = GetScalarizedVector(Op);
- }
EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BITCAST, SDLoc(N),
NewVT, Op);
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