[llvm] r322823 - [SelectionDAG] Convert assert to condtion

[Sam Parker via llvm-commits]

Author: sam_parker
Date: Thu Jan 18 01:22:24 2018
New Revision: 322823

URL: http://llvm.org/viewvc/llvm-project?rev=322823&view=rev
Log:
[SelectionDAG] Convert assert to condtion

Follow-up to r322120 which can cause assertions for AArch64 because
v1f64 and v1i64 are legal types.

Differential Revision: https://reviews.llvm.org/D42097

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=322823&r1=322822&r2=322823&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jan 18 01:22:24 2018
@@ -171,10 +171,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRe
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
   SDValue Op = N->getOperand(0);
   if (Op.getValueType().isVector()
-      && Op.getValueType().getVectorNumElements() == 1) {
-    assert(!isSimpleLegalType(Op.getValueType()));
+      && Op.getValueType().getVectorNumElements() == 1
+      && !isSimpleLegalType(Op.getValueType()))
     Op = GetScalarizedVector(Op);
-  }
   EVT NewVT = N->getValueType(0).getVectorElementType();
   return DAG.getNode(ISD::BITCAST, SDLoc(N),
                      NewVT, Op);