[PATCH] D34515: [ARM] Materialise some boolean values to avoid a branch
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 13:47:17 PST 2018
efriedma added a comment.
The use of clz is very similar to what the PowerPC backend does; I wonder if we can pick up any additional tricks from there.
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Comment at: lib/Target/ARM/ARMISelLowering.cpp:10015-10025
+ if (N->getOpcode() == ARMISD::SUBC) {
+ // (SUBC (ADDE 0, 0, C), 1) -> C
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ if (LHS->getOpcode() == ARMISD::ADDE &&
+ isNullConstant(LHS->getOperand(0)) &&
+ isNullConstant(LHS->getOperand(1)) && isOneConstant(RHS)) {
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rogfer01 wrote:
> I think this may make the `ADDC` combiner above redundant as `ADDC x, -1` will usually become `SUBC x, 1`. I'll try to see if I can remove the `ADDC` one.
Did you end up checking this?
================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:7443
+ if (isNullConstant(Carry))
+ return SDValue();
+
----------------
When do we hit this case? I would expect that normally DAGCombiner::visitADDCARRY would combine this away.
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Comment at: lib/Target/ARM/ARMISelLowering.cpp:12245
+ if (!VT.isInteger())
+ return SDValue();
----------------
Do we generate ARMISD::CMOV for values which aren't integers?
https://reviews.llvm.org/D34515
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