[llvm] r322106 - [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86.

[Hans Wennborg via llvm-commits]

Merged to 6.0 in r322680.

On Tue, Jan 9, 2018 at 8:08 PM, Alexey Bataev via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: abataev
> Date: Tue Jan  9 11:08:22 2018
> New Revision: 322106
>
> URL: http://llvm.org/viewvc/llvm-project?rev=322106&view=rev
> Log:
> [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86.
>
> Summary:
> If the vector type is transformed to non-vector single type, the compile
> may crash trying to get vector information about non-vector type.
>
> Reviewers: RKSimon, spatel, mkuper, hfinkel
>
> Subscribers: llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D41862
>
> Added:
>     llvm/trunk/test/Transforms/SLPVectorizer/X86/PR35865.ll
> Modified:
>     llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=322106&r1=322105&r2=322106&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Tue Jan  9 11:08:22 2018
> @@ -754,7 +754,8 @@ int X86TTIImpl::getShuffleCost(TTI::Shuf
>    // type remains the same.
>    if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
>      MVT LegalVT = LT.second;
> -    if (LegalVT.getVectorElementType().getSizeInBits() ==
> +    if (LegalVT.isVector() &&
> +        LegalVT.getVectorElementType().getSizeInBits() ==
>              Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
>          LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
>
>
> Added: llvm/trunk/test/Transforms/SLPVectorizer/X86/PR35865.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/X86/PR35865.ll?rev=322106&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/SLPVectorizer/X86/PR35865.ll (added)
> +++ llvm/trunk/test/Transforms/SLPVectorizer/X86/PR35865.ll Tue Jan  9 11:08:22 2018
> @@ -0,0 +1,27 @@
> +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
> +; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
> +
> +define void @_Z10fooConvertPDv4_xS0_S0_PKS_() {
> +; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_(
> +; CHECK-NEXT:  entry:
> +; CHECK-NEXT:    [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4
> +; CHECK-NEXT:    [[CONV_I_4_I:%.*]] = fpext half [[TMP0]] to float
> +; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float [[CONV_I_4_I]] to i32
> +; CHECK-NEXT:    [[VECINS_I_4_I:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 4
> +; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x half> undef, i32 5
> +; CHECK-NEXT:    [[CONV_I_5_I:%.*]] = fpext half [[TMP2]] to float
> +; CHECK-NEXT:    [[TMP3:%.*]] = bitcast float [[CONV_I_5_I]] to i32
> +; CHECK-NEXT:    [[VECINS_I_5_I:%.*]] = insertelement <8 x i32> [[VECINS_I_4_I]], i32 [[TMP3]], i32 5
> +; CHECK-NEXT:    ret void
> +;
> +entry:
> +  %0 = extractelement <16 x half> undef, i32 4
> +  %conv.i.4.i = fpext half %0 to float
> +  %1 = bitcast float %conv.i.4.i to i32
> +  %vecins.i.4.i = insertelement <8 x i32> undef, i32 %1, i32 4
> +  %2 = extractelement <16 x half> undef, i32 5
> +  %conv.i.5.i = fpext half %2 to float
> +  %3 = bitcast float %conv.i.5.i to i32
> +  %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5
> +  ret void
> +}
>
>
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