[llvm] r322662 - [InstCombine] fix demanded-bits propagation for zext/trunc

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Jan 17 06:39:28 2018
New Revision: 322662

URL: http://llvm.org/viewvc/llvm-project?rev=322662&view=rev
Log:
[InstCombine] fix demanded-bits propagation for zext/trunc

I was comparing the demanded-bits implementations between InstCombine
and TargetLowering as part of investigating questions in D42088 and
noticed that this was wrong in IR. We were losing all of the prior
known bits when we got back to the 'zext'.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    llvm/trunk/test/Transforms/InstCombine/and.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=322662&r1=322661&r2=322662&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Wed Jan 17 06:39:28 2018
@@ -333,7 +333,7 @@ Value *InstCombiner::SimplifyDemandedUse
     KnownBits InputKnown(SrcBitWidth);
     if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
       return I;
-    Known = Known.zextOrTrunc(BitWidth);
+    Known = InputKnown.zextOrTrunc(BitWidth);
     // Any top bits are known to be zero.
     if (BitWidth > SrcBitWidth)
       Known.Zero.setBitsFrom(SrcBitWidth);

Modified: llvm/trunk/test/Transforms/InstCombine/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/and.ll?rev=322662&r1=322661&r2=322662&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/and.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/and.ll Wed Jan 17 06:39:28 2018
@@ -376,9 +376,7 @@ define i32 @and_zext_demanded(i16 %x, i3
 ; CHECK-LABEL: @and_zext_demanded(
 ; CHECK-NEXT:    [[S:%.*]] = lshr i16 %x, 8
 ; CHECK-NEXT:    [[Z:%.*]] = zext i16 [[S]] to i32
-; CHECK-NEXT:    [[O:%.*]] = or i32 %y, 255
-; CHECK-NEXT:    [[A:%.*]] = and i32 [[O]], [[Z]]
-; CHECK-NEXT:    ret i32 [[A]]
+; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %s = lshr i16 %x, 8
   %z = zext i16 %s to i32