[llvm] r322657 - [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR

[Diana Picus via llvm-commits]

Author: rovka
Date: Wed Jan 17 06:14:14 2018
New Revision: 322657

URL: http://llvm.org/viewvc/llvm-project?rev=322657&view=rev
Log:
[ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=322657&r1=322656&r2=322657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Wed Jan 17 06:14:14 2018
@@ -285,6 +285,24 @@ ARMRegisterBankInfo::getInstrMapping(con
                                   &ARM::ValueMappings[ARM::SPR3OpsIdx]});
     break;
   }
+  case G_FPEXT: {
+    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+    if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32)
+      OperandsMapping =
+          getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
+                              &ARM::ValueMappings[ARM::SPR3OpsIdx]});
+    break;
+  }
+  case G_FPTRUNC: {
+    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+    if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64)
+      OperandsMapping =
+          getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
+                              &ARM::ValueMappings[ARM::DPR3OpsIdx]});
+    break;
+  }
   case G_CONSTANT:
   case G_FRAME_INDEX:
   case G_GLOBAL_VALUE:

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=322657&r1=322656&r2=322657&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Wed Jan 17 06:14:14 2018
@@ -65,6 +65,9 @@
   define void @test_fma_s32() #2 { ret void }
   define void @test_fma_s64() #2 { ret void }
 
+  define void @test_fpext_s32_to_s64() #0 { ret void }
+  define void @test_fptrunc_s64_to_s32() #0 { ret void }
+
   define void @test_soft_fp_s64() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2"}
@@ -1198,6 +1201,48 @@ body:             |
     BX_RET 14, %noreg, implicit %d0
 ...
 ---
+name:            test_fpext_s32_to_s64
+# CHECK-LABEL: name: test_fpext_s32_to_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %s0
+
+    %0(s32) = COPY %s0
+    %1(s64) = G_FPEXT %0
+    %d0 = COPY %1(s64)
+    BX_RET 14, %noreg, implicit %d0
+...
+---
+name:            test_fptrunc_s64_to_s32
+# CHECK-LABEL: name: test_fptrunc_s64_to_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %d0
+
+    %0(s64) = COPY %d0
+    %1(s32) = G_FPTRUNC %0
+    %s0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %s0
+...
+---
 name:            test_soft_fp_s64
 # CHECK-LABEL: name: test_soft_fp_s64
 legalized:       true