[PATCH] D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian

[Oliver Stannard via Phabricator via llvm-commits]

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM, thanks.

I've spotted a missed optimisation in the tests, but that should be done as a separate patch.



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Comment at: test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll:70
 define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev64 v{{[0-9]+}}.4h
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It looks like we generate more efficient code for the v4i16 case than the v4f16 case above. Is there a way we could get better code here? I think this is just an optimisation, so makes sense to do it as a separate patch (or raise a ticket if you don't have time to do it now).


Repository:
  rL LLVM

https://reviews.llvm.org/D41863