[PATCH] D41905: [ARM] Add support for unpredictable MVN instructions.

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added inline comments.


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Comment at: lib/Target/ARM/ARMInstrInfo.td:3925
 }
-def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
+def  MVNsr  : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
                   DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
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The register class changes will also affect assembly, could you add tests for them?


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Comment at: test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt:3
+
+# CHECK: potentially undefined
+# CHECK: 0x03 0x20 0xe1 0xe1
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Could you add comments to these showing which instructions they are, and which fields are invalid?


https://reviews.llvm.org/D41905