[PATCH] D42159: [GlobalISel] Making MachineCSE runable in the middle of the GlobalISel

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin created this revision.
rtereshin added reviewers: qcolombet, void.
Herald added subscribers: llvm-commits, javed.absar, kristof.beyls, rovka.

Right now, it is not possible to run MachineCSE in the middle of the
GlobalISel pipeline. Being able to run generic optimizations between the
core passes of GlobalISel was one of the goals of the new ISel framework.
This is the first attempt to do it in a POC manner.

The problem is that MachineCSE pass assumes all register operands have a
register class, which, in GlobalISel context, won't be true until after the
InstructionSelect pass. The reason for this behaviour is that before
replacing one virtual register with another, MachineCSE pass (and most of
the other optimization machine passes) must check if the virtual registers'
constraints have a (sufficiently large) intersection, and constrain the
resulting register appropriately if such intersection exists.

GlobalISel extends the representation of such constraints from just a
register class to a tripple (low-level type, register bank, register
class).

This commit adds MachineRegisterInfo::constrainRegAttrs method that extends
MachineRegisterInfo::constrainRegClass to such a tripple.

The idea is that going forward we should use:

- RegisterBankInfo::constrainGenericRegister within GlobalISel's InstructionSelect pass
- MachineRegisterInfo::constrainRegClass within SelectionDAG ISel
- MachineRegisterInfo::constrainRegAttrs everywhere else

regardless the target and instruction selector it uses.

For that reason I tried to keep the performance overhead of
constrainRegAttrs comparing to constrainRegClass at a minimum, hence the
helper method.


Repository:
  rL LLVM

https://reviews.llvm.org/D42159

Files:
  include/llvm/CodeGen/MachineRegisterInfo.h
  lib/CodeGen/MachineCSE.cpp
  lib/CodeGen/MachineRegisterInfo.cpp
  test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir

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