[PATCH] D41233: [InstCombine] Canonizing 'and' before 'shl'

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I know smaller constants is meaningful to X86. But do other targets have different immediate sizes for And instructions. ARM encodes immediates with a shift amount applied to them I think? Not sure about others.



================
Comment at: lib/Transforms/InstCombine/InstCombineShifts.cpp:554
       const APInt *C;
       if (!isa<Constant>(FalseVal) && TBO->getOperand(0) == FalseVal &&
           match(TBO->getOperand(1), m_APInt(C)) &&
----------------
This transform is very similar to the one above, but the binop here is conditional. Should we be avoid pulling shifts above a conditional and?


Repository:
  rL LLVM

https://reviews.llvm.org/D41233