[PATCH] D42104: [AArch64] Generate the CASP instruction for 128-bit cmpxchg

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
olista01 added reviewers: rengolin, t.p.northover, christof.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

The Large System Extension added an atomic compare-and-swap instruction
that operates on a pair of 64-bit registers, which we can use to
implement a 128-bit cmpxchg.

Because i128 is not a legal type for AArch64 we have to do all of the
instruction selection in C++, and the instruction requires even/odd
register pairs, so we have to wrap it in REG_SEQUENCE and EXTRACT_SUBREG
nodes. This is very similar to what we do for 64-bit cmpxchg in the ARM
backend.


Repository:
  rL LLVM

https://reviews.llvm.org/D42104

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  test/CodeGen/AArch64/atomic-ops-lse.ll

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