[PATCH] D42097: [SelectionDAG] Convert assert to condtion

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: tpr, arsenm.
Herald added subscribers: kristof.beyls, wdng, aemerson.

Follow-up to https://reviews.llvm.org/D41126, which can cause assertions for AArch64 because v1f64 and v1i64 are legal types.


https://reviews.llvm.org/D42097

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp


Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -171,10 +171,9 @@
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
   SDValue Op = N->getOperand(0);
   if (Op.getValueType().isVector()
-      && Op.getValueType().getVectorNumElements() == 1) {
-    assert(!isSimpleLegalType(Op.getValueType()));
+      && Op.getValueType().getVectorNumElements() == 1
+      && !isSimpleLegalType(Op.getValueType()))
     Op = GetScalarizedVector(Op);
-  }
   EVT NewVT = N->getValueType(0).getVectorElementType();
   return DAG.getNode(ISD::BITCAST, SDLoc(N),
                      NewVT, Op);


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