[PATCH] D41967: [PPC] Add a new register XER aliased to CARRY

[Guozhi Wei via Phabricator via llvm-commits]

Carrot updated this revision to Diff 129700.
Carrot retitled this revision from "[PPC] Return PPC::CARRY for inline asm constraint "{xer}"" to "[PPC] Add a new register XER aliased to CARRY".
Carrot edited the summary of this revision.
Carrot added a comment.

The aliased register XER should also be put into register class CARRYRC, then getRegForInlineAsmConstraint can find it.


https://reviews.llvm.org/D41967

Files:
  lib/Target/PowerPC/PPCRegisterInfo.td


Index: lib/Target/PowerPC/PPCRegisterInfo.td
===================================================================
--- lib/Target/PowerPC/PPCRegisterInfo.td
+++ lib/Target/PowerPC/PPCRegisterInfo.td
@@ -208,10 +208,14 @@
 // VRsave register
 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
 
+def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
+
 // Carry bit.  In the architecture this is really bit 0 of the XER register
 // (which really is SPR register 1);  this is the only bit interesting to a
 // compiler.
-def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
+def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
+  let Aliases = [XER];
+}
 
 // FP rounding mode:  bits 30 and 31 of the FP status and control register
 // This is not allocated as a normal register; it appears only in
@@ -351,7 +355,7 @@
 }
 
 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
-def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
+def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
   let CopyCost = -1;
 }
 


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