[PATCH] D41908: [X86][MMX] Add support for MMX zero vector creation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

This seems to cause a constant pool to be use for the second _mm_setzero_si64 call.

  #include <x86intrin.h>
  
  __m64 bar(__m64 a, __m64 b, __m64 z, __m64 y) {
    __m64 c = _mm_add_pi32(a, b);
    __m64 d = _mm_mul_su32(c, _mm_setzero_si64());
    __m64 e = _mm_add_pi32(d, z);
    __m64 f = _mm_add_pi16(a, e);
    __m64 g = _mm_add_pi16(b, f);
    __m64 h = _mm_mul_su32(g, y);
    __m64 i = _mm_add_pi16(h, z);
    __m64 j = _mm_add_pi16(i, y);
    __m64 k = _mm_add_pi16(j, e);
    __m64 l = _mm_add_pi16(k, f);
    __m64 m = _mm_add_pi16(l, d);
    __m64 n = _mm_mul_su32(m, c);
    __m64 o = _mm_add_pi16(n, _mm_setzero_si64());
    __m64 p = _mm_add_pi16(o, g);
    __m64 q = _mm_mul_su32(p, i);
    __m64 r = _mm_mul_su32(q, b);
    __m64 s = _mm_add_pi16(r, j);
    __m64 t = _mm_add_pi16(s, k);
    return t;
  }


Repository:
  rL LLVM

https://reviews.llvm.org/D41908