[PATCH] D41944: [LLVM][IR][LIT] support of 'no-overflow' flag for sdiv\udiv instructions
Mohammed Agabaria via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 03:29:36 PST 2018
magabari created this revision.
magabari added reviewers: zvi, erichkeane.
Herald added subscribers: llvm-commits, sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar, asb, fedor.sergeev, kbarton, aheejin, eraman, jgravelle-google, sbc100, javed.absar, nhaehnle, nemanjai, sdardis, mehdi_amini, dylanmckay, jyknight, dschuff, sanjoy, jfb, qcolombet, MatzeB, jholewinski.
Following to the discussion made in RFC: https://groups.google.com/forum/#!msg/llvm-dev/eFtnCwpMMhs/eAHQj8rJCAAJ;context-place=searchin/llvm-dev/magabari%7Csort:date
This is an implementation of 'nof' flag for sdiv\udiv llvm instructions.
Please start reading the proposed RFC & changes in the LangRef.rst.
Adding this flag to integer div flag will allow us (later) to speculate div operation without a need to worry of divide by zero or overflow.
This patch contains llvm frontend changes only.
Repository:
rL LLVM
https://reviews.llvm.org/D41944
Files:
docs/LangRef.rst
include/llvm/Analysis/TargetFolder.h
include/llvm/Analysis/TargetTransformInfo.h
include/llvm/Analysis/TargetTransformInfoImpl.h
include/llvm/Bitcode/LLVMBitCodes.h
include/llvm/IR/ConstantFolder.h
include/llvm/IR/Constants.h
include/llvm/IR/IRBuilder.h
include/llvm/IR/InstrTypes.h
include/llvm/IR/Instruction.h
include/llvm/IR/NoFolder.h
include/llvm/IR/Operator.h
lib/Analysis/TargetTransformInfo.cpp
lib/AsmParser/LLLexer.cpp
lib/AsmParser/LLParser.cpp
lib/AsmParser/LLToken.h
lib/Bitcode/Reader/BitcodeReader.cpp
lib/Bitcode/Writer/BitcodeWriter.cpp
lib/IR/AsmWriter.cpp
lib/IR/Constants.cpp
lib/IR/Instruction.cpp
lib/Target/X86/X86TargetTransformInfo.cpp
lib/Target/X86/X86TargetTransformInfo.h
lib/Transforms/InstCombine/InstCombineAddSub.cpp
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
lib/Transforms/InstCombine/InstCombineVectorOps.cpp
lib/Transforms/InstCombine/InstructionCombining.cpp
lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
lib/Transforms/Utils/SimplifyIndVar.cpp
test/Analysis/CostModel/AArch64/free-widening-casts.ll
test/Analysis/CostModel/ARM/divrem.ll
test/Analysis/CostModel/SystemZ/div-pow2.ll
test/Analysis/CostModel/SystemZ/int-arith.ll
test/Analysis/CostModel/SystemZ/memop-folding-int-arith.ll
test/Analysis/CostModel/X86/div.ll
test/Analysis/CostModel/X86/vdiv-cost.ll
test/Analysis/DependenceAnalysis/BasePtrBug.ll
test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll
test/Analysis/Lint/check-zero-divide.ll
test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
test/Analysis/ScalarEvolution/avoid-smax-1.ll
test/Analysis/ScalarEvolution/flags-from-poison.ll
test/Analysis/ScalarEvolution/flattened-0.ll
test/Analysis/ScalarEvolution/implied-via-division.ll
test/Analysis/ScalarEvolution/undefined.ll
test/Analysis/ValueTracking/known-power-of-two.ll
test/Assembler/ConstantExprFold.ll
test/Assembler/flags.ll
test/Bindings/llvm-c/echo.ll
test/Bitcode/compatibility.ll
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
test/CodeGen/AArch64/analyzecmp.ll
test/CodeGen/AArch64/arm64-arith.ll
test/CodeGen/AArch64/arm64-ccmp.ll
test/CodeGen/AArch64/arm64-fast-isel.ll
test/CodeGen/AArch64/arm64-misched-basic-A57.ll
test/CodeGen/AArch64/arm64-neon-mul-div.ll
test/CodeGen/AArch64/div_minsize.ll
test/CodeGen/AArch64/divrem.ll
test/CodeGen/AArch64/dp2.ll
test/CodeGen/AArch64/fast-isel-sdiv.ll
test/CodeGen/AArch64/rem_crash.ll
test/CodeGen/AArch64/sdivpow2.ll
test/CodeGen/AMDGPU/lds-oqap-crash.ll
test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
test/CodeGen/AMDGPU/r600cfg.ll
test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
test/CodeGen/AMDGPU/sdiv.ll
test/CodeGen/AMDGPU/sdivrem24.ll
test/CodeGen/AMDGPU/sdivrem64.ll
test/CodeGen/AMDGPU/sgprcopies.ll
test/CodeGen/AMDGPU/structurize.ll
test/CodeGen/AMDGPU/udiv.ll
test/CodeGen/AMDGPU/udivrem.ll
test/CodeGen/AMDGPU/udivrem24.ll
test/CodeGen/AMDGPU/udivrem64.ll
test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
test/CodeGen/ARM/2011-08-29-SchedCycle.ll
test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
test/CodeGen/ARM/2012-05-04-vmov.ll
test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
test/CodeGen/ARM/Windows/dbzchk.ll
test/CodeGen/ARM/Windows/division-range.ll
test/CodeGen/ARM/Windows/division.ll
test/CodeGen/ARM/Windows/no-aeabi.ll
test/CodeGen/ARM/adv-copy-opt.ll
test/CodeGen/ARM/call-tc.ll
test/CodeGen/ARM/cortex-a57-misched-basic.ll
test/CodeGen/ARM/cortexr52-misched-basic.ll
test/CodeGen/ARM/data-in-code-annotations.ll
test/CodeGen/ARM/div.ll
test/CodeGen/ARM/divmod-eabi.ll
test/CodeGen/ARM/divmod.ll
test/CodeGen/ARM/fast-isel-call.ll
test/CodeGen/ARM/jumptable-label.ll
test/CodeGen/ARM/krait-cpu-div-attribute.ll
test/CodeGen/ARM/local-call.ll
test/CodeGen/ARM/mulhi.ll
test/CodeGen/ARM/neon_div.ll
test/CodeGen/ARM/rem_crash.ll
test/CodeGen/ARM/select-imm.ll
test/CodeGen/ARM/thumb1-div.ll
test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
test/CodeGen/ARM/urem-opt-size.ll
test/CodeGen/ARM/vector-extend-narrow.ll
test/CodeGen/ARM/vector-promotion.ll
test/CodeGen/AVR/div.ll
test/CodeGen/BPF/sanity.ll
test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
test/CodeGen/Generic/BasicInstrs.ll
test/CodeGen/Generic/div-neg-power-2.ll
test/CodeGen/Generic/print-arith-int.ll
test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
test/CodeGen/Hexagon/macint.ll
test/CodeGen/Hexagon/multi-cycle.ll
test/CodeGen/Hexagon/swp-max.ll
test/CodeGen/Lanai/i32.ll
test/CodeGen/MIR/X86/dynamic-regmask.ll
test/CodeGen/MSP430/2009-11-20-NewNode.ll
test/CodeGen/MSP430/libcalls.ll
test/CodeGen/Mips/Fast-ISel/div1.ll
test/CodeGen/Mips/assertzext-trunc.ll
test/CodeGen/Mips/div.ll
test/CodeGen/Mips/div_rem.ll
test/CodeGen/Mips/divrem.ll
test/CodeGen/Mips/divu.ll
test/CodeGen/Mips/divu_remu.ll
test/CodeGen/Mips/llvm-ir/sdiv.ll
test/CodeGen/Mips/llvm-ir/udiv.ll
test/CodeGen/Mips/mips64instrs.ll
test/CodeGen/Mips/mips64muldiv.ll
test/CodeGen/Mips/msa/3r-d.ll
test/CodeGen/Mips/msa/arithmetic.ll
test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
test/CodeGen/NVPTX/arithmetic-int.ll
test/CodeGen/NVPTX/bypass-div.ll
test/CodeGen/NVPTX/divrem-combine.ll
test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
test/CodeGen/PowerPC/PR33636.ll
test/CodeGen/PowerPC/ctrloop-i64.ll
test/CodeGen/PowerPC/ctrloop-intrin.ll
test/CodeGen/PowerPC/ctrloop-udivti3.ll
test/CodeGen/PowerPC/div-2.ll
test/CodeGen/PowerPC/expand-foldable-isel.ll
test/CodeGen/PowerPC/fast-isel-call.ll
test/CodeGen/PowerPC/ppc64-P9-mod.ll
test/CodeGen/PowerPC/ppc64-r2-alloc.ll
test/CodeGen/PowerPC/pr26690.ll
test/CodeGen/PowerPC/sdiv-pow2.ll
test/CodeGen/PowerPC/select_const.ll
test/CodeGen/RISCV/div.ll
test/CodeGen/SPARC/64bit.ll
test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll
test/CodeGen/SPARC/basictest.ll
test/CodeGen/SPARC/multiple-div.ll
test/CodeGen/SPARC/soft-mul-div.ll
test/CodeGen/SystemZ/copy-physreg-128.ll
test/CodeGen/SystemZ/expand-zext-pseudo.ll
test/CodeGen/SystemZ/int-div-01.ll
test/CodeGen/SystemZ/int-div-02.ll
test/CodeGen/SystemZ/int-div-03.ll
test/CodeGen/SystemZ/int-div-04.ll
test/CodeGen/SystemZ/int-div-05.ll
test/CodeGen/SystemZ/int-div-06.ll
test/CodeGen/SystemZ/int-mul-08.ll
test/CodeGen/SystemZ/list-ilp-crash.ll
test/CodeGen/SystemZ/loop-03.ll
test/CodeGen/SystemZ/splitMove_undefReg_mverifier.ll
test/CodeGen/SystemZ/splitMove_undefReg_mverifier_2.ll
test/CodeGen/SystemZ/vec-div-01.ll
test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
test/CodeGen/Thumb/thumb-shrink-wrapping.ll
test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
test/CodeGen/Thumb2/div.ll
test/CodeGen/Thumb2/thumb2-select.ll
test/CodeGen/WebAssembly/divrem-constant.ll
test/CodeGen/WebAssembly/i128.ll
test/CodeGen/WebAssembly/i32.ll
test/CodeGen/WebAssembly/i64.ll
test/CodeGen/WebAssembly/phi.ll
test/CodeGen/WebAssembly/reg-stackify.ll
test/CodeGen/X86/2006-11-17-IllegalMove.ll
test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
test/CodeGen/X86/2008-04-16-CoalescerBug.ll
test/CodeGen/X86/2008-04-28-CoalescerBug.ll
test/CodeGen/X86/2009-02-08-CoalescerBug.ll
test/CodeGen/X86/2009-10-25-RewriterBug.ll
test/CodeGen/X86/2010-03-04-Mul8Bug.ll
test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll
test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
test/CodeGen/X86/2011-06-03-x87chain.ll
test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
test/CodeGen/X86/alldiv-divdi3.ll
test/CodeGen/X86/anyext.ll
test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll
test/CodeGen/X86/avx512-bugfix-23634.ll
test/CodeGen/X86/bypass-slow-division-32.ll
test/CodeGen/X86/bypass-slow-division-64.ll
test/CodeGen/X86/bypass-slow-division-tune.ll
test/CodeGen/X86/coalescer-identity.ll
test/CodeGen/X86/combine-sdiv.ll
test/CodeGen/X86/combine-udiv.ll
test/CodeGen/X86/crash-O0.ll
test/CodeGen/X86/crash-lre-eliminate-dead-def.ll
test/CodeGen/X86/crash.ll
test/CodeGen/X86/div-rem-simplify.ll
test/CodeGen/X86/div8.ll
test/CodeGen/X86/divide-by-constant.ll
test/CodeGen/X86/divide-windows-itanium.ll
test/CodeGen/X86/divrem.ll
test/CodeGen/X86/divrem8_ext.ll
test/CodeGen/X86/early-ifcvt.ll
test/CodeGen/X86/fast-isel-divrem-x86-64.ll
test/CodeGen/X86/fast-isel-divrem.ll
test/CodeGen/X86/fast-isel-x86-64.ll
test/CodeGen/X86/fold-vector-shuffle-crash.ll
test/CodeGen/X86/greedy_regalloc_bad_eviction_sequence.ll
test/CodeGen/X86/handle-move.ll
test/CodeGen/X86/hoist-invariant-load.ll
test/CodeGen/X86/i128-sdiv.ll
test/CodeGen/X86/known-bits-vector.ll
test/CodeGen/X86/known-bits.ll
test/CodeGen/X86/legalizedag_vec.ll
test/CodeGen/X86/libcall-sret.ll
test/CodeGen/X86/lsr-normalization.ll
test/CodeGen/X86/misched-new.ll
test/CodeGen/X86/optimize-max-0.ll
test/CodeGen/X86/phys_subreg_coalesce-2.ll
test/CodeGen/X86/pr14088.ll
test/CodeGen/X86/pr16807.ll
(184 more files...)
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