[llvm] r322354 - [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 22:21:36 PST 2018
Author: ctopper
Date: Thu Jan 11 22:21:36 2018
New Revision: 322354
URL: http://llvm.org/viewvc/llvm-project?rev=322354&view=rev
Log:
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.
While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/CodeGen/X86/stack-folding-tbm.ll
llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll
llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
llvm/trunk/test/CodeGen/X86/tbm-schedule.ll
llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/X86/x86_64-tbm-encoding.s
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jan 11 22:21:36 2018
@@ -2520,10 +2520,10 @@ multiclass tbm_ternary_imm_intr<bits<8>
IIC_BIN_MEM>, XOP, XOPA, Sched<[WriteALULd, ReadAfterLd]>;
}
-defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
+defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr{l}", i32mem, loadi32,
int_x86_tbm_bextri_u32, i32imm, imm>;
let ImmT = Imm32S in
-defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
+defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr{q}", i64mem, loadi64,
int_x86_tbm_bextri_u64, i64i32imm,
i64immSExt32>, VEX_W;
@@ -2543,10 +2543,10 @@ let hasSideEffects = 0 in {
multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
Format FormReg, Format FormMem> {
- defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
- loadi32>;
- defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
- loadi64>, VEX_W;
+ defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}",
+ i32mem, loadi32>;
+ defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}",
+ i64mem, loadi64>, VEX_W;
}
defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
Modified: llvm/trunk/test/CodeGen/X86/stack-folding-tbm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-tbm.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-folding-tbm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/stack-folding-tbm.ll Thu Jan 11 22:21:36 2018
@@ -11,7 +11,7 @@ target triple = "x86_64-unknown-unknown"
define i32 @stack_fold_bextri_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_bextri_u32
;CHECK: # %bb.0:
- ;CHECK: bextr $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: bextrl $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a0, i32 2814)
ret i32 %2
@@ -21,7 +21,7 @@ declare i32 @llvm.x86.tbm.bextri.u32(i32
define i64 @stack_fold_bextri_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_bextri_u64
;CHECK: # %bb.0:
- ;CHECK: bextr $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: bextrq $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a0, i64 2814)
ret i64 %2
@@ -30,7 +30,7 @@ declare i64 @llvm.x86.tbm.bextri.u64(i64
define i32 @stack_fold_blcfill_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcfill_u32
- ;CHECK: blcfill {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blcfilll {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = and i32 %a0, %2
@@ -39,7 +39,7 @@ define i32 @stack_fold_blcfill_u32(i32 %
define i64 @stack_fold_blcfill_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcfill_u64
- ;CHECK: blcfill {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blcfillq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = and i64 %a0, %2
@@ -48,7 +48,7 @@ define i64 @stack_fold_blcfill_u64(i64 %
define i32 @stack_fold_blci_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blci_u32
- ;CHECK: blci {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blcil {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %2, -1
@@ -58,7 +58,7 @@ define i32 @stack_fold_blci_u32(i32 %a0)
define i64 @stack_fold_blci_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blci_u64
- ;CHECK: blci {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blciq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %2, -1
@@ -68,7 +68,7 @@ define i64 @stack_fold_blci_u64(i64 %a0)
define i32 @stack_fold_blcic_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcic_u32
- ;CHECK: blcic {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blcicl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, -1
@@ -78,7 +78,7 @@ define i32 @stack_fold_blcic_u32(i32 %a0
define i64 @stack_fold_blcic_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcic_u64
- ;CHECK: blcic {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blcicq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, -1
@@ -88,7 +88,7 @@ define i64 @stack_fold_blcic_u64(i64 %a0
define i32 @stack_fold_blcmsk_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcmsk_u32
- ;CHECK: blcmsk {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blcmskl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, %2
@@ -97,7 +97,7 @@ define i32 @stack_fold_blcmsk_u32(i32 %a
define i64 @stack_fold_blcmsk_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcmsk_u64
- ;CHECK: blcmsk {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blcmskq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, %2
@@ -106,7 +106,7 @@ define i64 @stack_fold_blcmsk_u64(i64 %a
define i32 @stack_fold_blcs_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcs_u32
- ;CHECK: blcs {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blcsl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = or i32 %a0, %2
@@ -115,7 +115,7 @@ define i32 @stack_fold_blcs_u32(i32 %a0)
define i64 @stack_fold_blcs_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcs_u64
- ;CHECK: blcs {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blcsq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = or i64 %a0, %2
@@ -124,7 +124,7 @@ define i64 @stack_fold_blcs_u64(i64 %a0)
define i32 @stack_fold_blsfill_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blsfill_u32
- ;CHECK: blsfill {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blsfilll {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = or i32 %a0, %2
@@ -133,7 +133,7 @@ define i32 @stack_fold_blsfill_u32(i32 %
define i64 @stack_fold_blsfill_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blsfill_u64
- ;CHECK: blsfill {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blsfillq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = or i64 %a0, %2
@@ -142,7 +142,7 @@ define i64 @stack_fold_blsfill_u64(i64 %
define i32 @stack_fold_blsic_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blsic_u32
- ;CHECK: blsic {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: blsicl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = xor i32 %a0, -1
@@ -152,7 +152,7 @@ define i32 @stack_fold_blsic_u32(i32 %a0
define i64 @stack_fold_blsic_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blsic_u64
- ;CHECK: blsic {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: blsicq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = xor i64 %a0, -1
@@ -162,7 +162,7 @@ define i64 @stack_fold_blsic_u64(i64 %a0
define i32 @stack_fold_t1mskc_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_t1mskc_u32
- ;CHECK: t1mskc {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: t1mskcl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, -1
@@ -172,7 +172,7 @@ define i32 @stack_fold_t1mskc_u32(i32 %a
define i64 @stack_fold_t1mskc_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_t1mskc_u64
- ;CHECK: t1mskc {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: t1mskcq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, -1
@@ -182,7 +182,7 @@ define i64 @stack_fold_t1mskc_u64(i64 %a
define i32 @stack_fold_tzmsk_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_tzmsk_u32
- ;CHECK: tzmsk {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+ ;CHECK: tzmskl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = xor i32 %a0, -1
@@ -192,7 +192,7 @@ define i32 @stack_fold_tzmsk_u32(i32 %a0
define i64 @stack_fold_tzmsk_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_tzmsk_u64
- ;CHECK: tzmsk {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+ ;CHECK: tzmskq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = xor i64 %a0, -1
Modified: llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll Thu Jan 11 22:21:36 2018
@@ -6,7 +6,7 @@
define i64 @test__bextri_u64(i64 %a0) {
; X64-LABEL: test__bextri_u64:
; X64: # %bb.0:
-; X64-NEXT: bextr $1, %rdi, %rax
+; X64-NEXT: bextrq $1, %rdi, %rax
; X64-NEXT: retq
%1 = call i64 @llvm.x86.tbm.bextri.u64(i64 %a0, i64 1)
ret i64 %1
Modified: llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll Thu Jan 11 22:21:36 2018
@@ -7,12 +7,12 @@
define i32 @test__bextri_u32(i32 %a0) {
; X32-LABEL: test__bextri_u32:
; X32: # %bb.0:
-; X32-NEXT: bextr $1, {{[0-9]+}}(%esp), %eax
+; X32-NEXT: bextrl $1, {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
;
; X64-LABEL: test__bextri_u32:
; X64: # %bb.0:
-; X64-NEXT: bextr $1, %edi, %eax
+; X64-NEXT: bextrl $1, %edi, %eax
; X64-NEXT: retq
%1 = call i32 @llvm.x86.tbm.bextri.u32(i32 %a0, i32 1)
ret i32 %1
Modified: llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll Thu Jan 11 22:21:36 2018
@@ -4,7 +4,7 @@
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
; CHECK-LABEL: test_x86_tbm_bextri_u32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE
+; CHECK-NEXT: bextrl $2814, %edi, %eax # imm = 0xAFE
; CHECK-NEXT: retq
entry:
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814)
@@ -16,7 +16,7 @@ declare i32 @llvm.x86.tbm.bextri.u32(i32
define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, (%rdi), %eax # imm = 0xAFE
+; CHECK-NEXT: bextrl $2814, (%rdi), %eax # imm = 0xAFE
; CHECK-NEXT: retq
entry:
%tmp1 = load i32, i32* %a, align 4
@@ -27,7 +27,7 @@ entry:
define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind readonly {
; CHECK-LABEL: test_x86_tbm_bextri_u32_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE
+; CHECK-NEXT: bextrl $2814, %edi, %eax # imm = 0xAFE
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
entry:
@@ -40,7 +40,7 @@ entry:
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
; CHECK-LABEL: test_x86_tbm_bextri_u64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE
+; CHECK-NEXT: bextrq $2814, %rdi, %rax # imm = 0xAFE
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)
@@ -52,7 +52,7 @@ declare i64 @llvm.x86.tbm.bextri.u64(i64
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, (%rdi), %rax # imm = 0xAFE
+; CHECK-NEXT: bextrq $2814, (%rdi), %rax # imm = 0xAFE
; CHECK-NEXT: retq
entry:
%tmp1 = load i64, i64* %a, align 8
@@ -63,7 +63,7 @@ entry:
define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind readnone {
; CHECK-LABEL: test_x86_tbm_bextri_u64_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE
+; CHECK-NEXT: bextrq $2814, %rdi, %rax # imm = 0xAFE
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/tbm-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-schedule.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-schedule.ll Thu Jan 11 22:21:36 2018
@@ -7,17 +7,17 @@
define i32 @test_x86_tbm_bextri_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_bextri_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: bextr $3076, %edi, %ecx # imm = 0xC04
+; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
; GENERIC-NEXT: # sched: [1:0.33]
-; GENERIC-NEXT: bextr $3076, (%rsi), %eax # imm = 0xC04
+; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
; GENERIC-NEXT: # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_bextri_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: bextr $3076, %edi, %ecx # imm = 0xC04
-; BDVER-NEXT: bextr $3076, (%rsi), %eax # imm = 0xC04
+; BDVER-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
+; BDVER-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -32,17 +32,17 @@ define i32 @test_x86_tbm_bextri_u32(i32
define i64 @test_x86_tbm_bextri_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_bextri_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: bextr $3076, %edi, %ecx # imm = 0xC04
+; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
; GENERIC-NEXT: # sched: [1:0.33]
-; GENERIC-NEXT: bextr $3076, (%rsi), %eax # imm = 0xC04
+; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
; GENERIC-NEXT: # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_bextri_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: bextr $3076, %edi, %ecx # imm = 0xC04
-; BDVER-NEXT: bextr $3076, (%rsi), %eax # imm = 0xC04
+; BDVER-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
+; BDVER-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -57,15 +57,15 @@ define i64 @test_x86_tbm_bextri_u64(i64
define i32 @test_x86_tbm_blcfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcfill_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcfill %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blcfill (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blcfilll %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blcfilll (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcfill_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcfill %edi, %ecx
-; BDVER-NEXT: blcfill (%rsi), %eax
+; BDVER-NEXT: blcfilll %edi, %ecx
+; BDVER-NEXT: blcfilll (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -80,15 +80,15 @@ define i32 @test_x86_tbm_blcfill_u32(i32
define i64 @test_x86_tbm_blcfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcfill_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcfill %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blcfill (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blcfillq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blcfillq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcfill_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcfill %rdi, %rcx
-; BDVER-NEXT: blcfill (%rsi), %rax
+; BDVER-NEXT: blcfillq %rdi, %rcx
+; BDVER-NEXT: blcfillq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -103,15 +103,15 @@ define i64 @test_x86_tbm_blcfill_u64(i64
define i32 @test_x86_tbm_blci_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blci_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blci %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blci (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blcil %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blcil (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blci_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blci %edi, %ecx
-; BDVER-NEXT: blci (%rsi), %eax
+; BDVER-NEXT: blcil %edi, %ecx
+; BDVER-NEXT: blcil (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -128,15 +128,15 @@ define i32 @test_x86_tbm_blci_u32(i32 %a
define i64 @test_x86_tbm_blci_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blci_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blci %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blci (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blciq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blciq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blci_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blci %rdi, %rcx
-; BDVER-NEXT: blci (%rsi), %rax
+; BDVER-NEXT: blciq %rdi, %rcx
+; BDVER-NEXT: blciq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -153,15 +153,15 @@ define i64 @test_x86_tbm_blci_u64(i64 %a
define i32 @test_x86_tbm_blcic_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcic_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcic %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blcic (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blcicl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blcicl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcic_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcic %edi, %ecx
-; BDVER-NEXT: blcic (%rsi), %eax
+; BDVER-NEXT: blcicl %edi, %ecx
+; BDVER-NEXT: blcicl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -178,15 +178,15 @@ define i32 @test_x86_tbm_blcic_u32(i32 %
define i64 @test_x86_tbm_blcic_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcic_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcic %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blcic (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blcicq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blcicq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcic_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcic %rdi, %rcx
-; BDVER-NEXT: blcic (%rsi), %rax
+; BDVER-NEXT: blcicq %rdi, %rcx
+; BDVER-NEXT: blcicq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -203,15 +203,15 @@ define i64 @test_x86_tbm_blcic_u64(i64 %
define i32 @test_x86_tbm_blcmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcmsk_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcmsk %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blcmsk (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blcmskl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blcmskl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcmsk_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcmsk %edi, %ecx
-; BDVER-NEXT: blcmsk (%rsi), %eax
+; BDVER-NEXT: blcmskl %edi, %ecx
+; BDVER-NEXT: blcmskl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -226,15 +226,15 @@ define i32 @test_x86_tbm_blcmsk_u32(i32
define i64 @test_x86_tbm_blcmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcmsk_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcmsk %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blcmsk (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blcmskq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blcmskq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcmsk_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcmsk %rdi, %rcx
-; BDVER-NEXT: blcmsk (%rsi), %rax
+; BDVER-NEXT: blcmskq %rdi, %rcx
+; BDVER-NEXT: blcmskq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -249,15 +249,15 @@ define i64 @test_x86_tbm_blcmsk_u64(i64
define i32 @test_x86_tbm_blcs_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcs_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcs %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blcs (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blcsl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blcsl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcs_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcs %edi, %ecx
-; BDVER-NEXT: blcs (%rsi), %eax
+; BDVER-NEXT: blcsl %edi, %ecx
+; BDVER-NEXT: blcsl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -272,15 +272,15 @@ define i32 @test_x86_tbm_blcs_u32(i32 %a
define i64 @test_x86_tbm_blcs_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blcs_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blcs %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blcs (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blcsq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blcsq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blcs_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blcs %rdi, %rcx
-; BDVER-NEXT: blcs (%rsi), %rax
+; BDVER-NEXT: blcsq %rdi, %rcx
+; BDVER-NEXT: blcsq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -295,15 +295,15 @@ define i64 @test_x86_tbm_blcs_u64(i64 %a
define i32 @test_x86_tbm_blsfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blsfill_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blsfill %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blsfill (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blsfilll %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blsfilll (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blsfill_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blsfill %edi, %ecx
-; BDVER-NEXT: blsfill (%rsi), %eax
+; BDVER-NEXT: blsfilll %edi, %ecx
+; BDVER-NEXT: blsfilll (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -318,15 +318,15 @@ define i32 @test_x86_tbm_blsfill_u32(i32
define i64 @test_x86_tbm_blsfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blsfill_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blsfill %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blsfill (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blsfillq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blsfillq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blsfill_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blsfill %rdi, %rcx
-; BDVER-NEXT: blsfill (%rsi), %rax
+; BDVER-NEXT: blsfillq %rdi, %rcx
+; BDVER-NEXT: blsfillq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -341,15 +341,15 @@ define i64 @test_x86_tbm_blsfill_u64(i64
define i32 @test_x86_tbm_blsic_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blsic_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blsic %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: blsic (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: blsicl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: blsicl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blsic_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: blsic %edi, %ecx
-; BDVER-NEXT: blsic (%rsi), %eax
+; BDVER-NEXT: blsicl %edi, %ecx
+; BDVER-NEXT: blsicl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -366,15 +366,15 @@ define i32 @test_x86_tbm_blsic_u32(i32 %
define i64 @test_x86_tbm_blsic_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_blsic_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: blsic %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: blsic (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: blsicq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: blsicq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_blsic_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: blsic %rdi, %rcx
-; BDVER-NEXT: blsic (%rsi), %rax
+; BDVER-NEXT: blsicq %rdi, %rcx
+; BDVER-NEXT: blsicq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -391,15 +391,15 @@ define i64 @test_x86_tbm_blsic_u64(i64 %
define i32 @test_x86_tbm_t1mskc_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_t1mskc_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: t1mskc %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: t1mskc (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: t1mskcl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: t1mskcl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_t1mskc_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: t1mskc %edi, %ecx
-; BDVER-NEXT: t1mskc (%rsi), %eax
+; BDVER-NEXT: t1mskcl %edi, %ecx
+; BDVER-NEXT: t1mskcl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -416,15 +416,15 @@ define i32 @test_x86_tbm_t1mskc_u32(i32
define i64 @test_x86_tbm_t1mskc_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_t1mskc_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: t1mskc %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: t1mskc (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: t1mskcq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: t1mskcq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_t1mskc_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: t1mskc %rdi, %rcx
-; BDVER-NEXT: t1mskc (%rsi), %rax
+; BDVER-NEXT: t1mskcq %rdi, %rcx
+; BDVER-NEXT: t1mskcq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
@@ -441,15 +441,15 @@ define i64 @test_x86_tbm_t1mskc_u64(i64
define i32 @test_x86_tbm_tzmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_tzmsk_u32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: tzmsk %edi, %ecx # sched: [1:0.33]
-; GENERIC-NEXT: tzmsk (%rsi), %eax # sched: [5:0.50]
+; GENERIC-NEXT: tzmskl %edi, %ecx # sched: [1:0.33]
+; GENERIC-NEXT: tzmskl (%rsi), %eax # sched: [5:0.50]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_tzmsk_u32:
; BDVER: # %bb.0:
-; BDVER-NEXT: tzmsk %edi, %ecx
-; BDVER-NEXT: tzmsk (%rsi), %eax
+; BDVER-NEXT: tzmskl %edi, %ecx
+; BDVER-NEXT: tzmskl (%rsi), %eax
; BDVER-NEXT: addl %ecx, %eax
; BDVER-NEXT: retq
%a1 = load i32, i32* %p1
@@ -466,15 +466,15 @@ define i32 @test_x86_tbm_tzmsk_u32(i32 %
define i64 @test_x86_tbm_tzmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
; GENERIC-LABEL: test_x86_tbm_tzmsk_u64:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: tzmsk %rdi, %rcx # sched: [1:0.33]
-; GENERIC-NEXT: tzmsk (%rsi), %rax # sched: [5:0.50]
+; GENERIC-NEXT: tzmskq %rdi, %rcx # sched: [1:0.33]
+; GENERIC-NEXT: tzmskq (%rsi), %rax # sched: [5:0.50]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; BDVER-LABEL: test_x86_tbm_tzmsk_u64:
; BDVER: # %bb.0:
-; BDVER-NEXT: tzmsk %rdi, %rcx
-; BDVER-NEXT: tzmsk (%rsi), %rax
+; BDVER-NEXT: tzmskq %rdi, %rcx
+; BDVER-NEXT: tzmskq (%rsi), %rax
; BDVER-NEXT: addq %rcx, %rax
; BDVER-NEXT: retq
%a1 = load i64, i64* %p1
Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Thu Jan 11 22:21:36 2018
@@ -6,7 +6,7 @@
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04
; CHECK-NEXT: retq
%t0 = lshr i32 %a, 4
%t1 = and i32 %t0, 4095
@@ -28,7 +28,7 @@ define i32 @test_x86_tbm_bextri_u32_subr
define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, (%rdi), %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, (%rdi), %eax # imm = 0xC04
; CHECK-NEXT: retq
%t0 = load i32, i32* %a
%t1 = lshr i32 %t0, 4
@@ -39,7 +39,7 @@ define i32 @test_x86_tbm_bextri_u32_m(i3
define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = lshr i32 %a, 4
@@ -67,7 +67,7 @@ define i32 @test_x86_tbm_bextri_u32_z2(i
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04
; CHECK-NEXT: retq
%t0 = lshr i64 %a, 4
%t1 = and i64 %t0, 4095
@@ -89,7 +89,7 @@ define i64 @test_x86_tbm_bextri_u64_subr
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, (%rdi), %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, (%rdi), %eax # imm = 0xC04
; CHECK-NEXT: retq
%t0 = load i64, i64* %a
%t1 = lshr i64 %t0, 4
@@ -100,7 +100,7 @@ define i64 @test_x86_tbm_bextri_u64_m(i6
define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
+; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = lshr i64 %a, 4
@@ -128,7 +128,7 @@ define i64 @test_x86_tbm_bextri_u64_z2(i
define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcfill_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcfill %edi, %eax
+; CHECK-NEXT: blcfilll %edi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
%t1 = and i32 %t0, %a
@@ -138,7 +138,7 @@ define i32 @test_x86_tbm_blcfill_u32(i32
define i32 @test_x86_tbm_blcfill_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcfill_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcfill %edi, %eax
+; CHECK-NEXT: blcfilll %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -167,7 +167,7 @@ define i32 @test_x86_tbm_blcfill_u32_z2(
define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcfill_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcfill %rdi, %rax
+; CHECK-NEXT: blcfillq %rdi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
%t1 = and i64 %t0, %a
@@ -177,7 +177,7 @@ define i64 @test_x86_tbm_blcfill_u64(i64
define i64 @test_x86_tbm_blcfill_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcfill_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcfill %rdi, %rax
+; CHECK-NEXT: blcfillq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -205,7 +205,7 @@ define i64 @test_x86_tbm_blcfill_u64_z2(
define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %edi, %eax
+; CHECK-NEXT: blcil %edi, %eax
; CHECK-NEXT: retq
%t0 = add i32 1, %a
%t1 = xor i32 %t0, -1
@@ -216,7 +216,7 @@ define i32 @test_x86_tbm_blci_u32(i32 %a
define i32 @test_x86_tbm_blci_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %edi, %eax
+; CHECK-NEXT: blcil %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 1, %a
@@ -248,7 +248,7 @@ define i32 @test_x86_tbm_blci_u32_z2(i32
define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %rdi, %rax
+; CHECK-NEXT: blciq %rdi, %rax
; CHECK-NEXT: retq
%t0 = add i64 1, %a
%t1 = xor i64 %t0, -1
@@ -259,7 +259,7 @@ define i64 @test_x86_tbm_blci_u64(i64 %a
define i64 @test_x86_tbm_blci_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %rdi, %rax
+; CHECK-NEXT: blciq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 1, %a
@@ -290,7 +290,7 @@ define i64 @test_x86_tbm_blci_u64_z2(i64
define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u32_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %edi, %eax
+; CHECK-NEXT: blcil %edi, %eax
; CHECK-NEXT: retq
%t0 = sub i32 -2, %a
%t1 = or i32 %t0, %a
@@ -300,7 +300,7 @@ define i32 @test_x86_tbm_blci_u32_b(i32
define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blci_u64_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: blci %rdi, %rax
+; CHECK-NEXT: blciq %rdi, %rax
; CHECK-NEXT: retq
%t0 = sub i64 -2, %a
%t1 = or i64 %t0, %a
@@ -310,7 +310,7 @@ define i64 @test_x86_tbm_blci_u64_b(i64
define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcic_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcic %edi, %eax
+; CHECK-NEXT: blcicl %edi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
%t1 = add i32 %a, 1
@@ -321,7 +321,7 @@ define i32 @test_x86_tbm_blcic_u32(i32 %
define i32 @test_x86_tbm_blcic_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcic_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcic %edi, %eax
+; CHECK-NEXT: blcicl %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
@@ -353,7 +353,7 @@ define i32 @test_x86_tbm_blcic_u32_z2(i3
define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcic_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcic %rdi, %rax
+; CHECK-NEXT: blcicq %rdi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
%t1 = add i64 %a, 1
@@ -364,7 +364,7 @@ define i64 @test_x86_tbm_blcic_u64(i64 %
define i64 @test_x86_tbm_blcic_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcic_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcic %rdi, %rax
+; CHECK-NEXT: blcicq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
@@ -396,7 +396,7 @@ define i64 @test_x86_tbm_blcic_u64_z2(i6
define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcmsk %edi, %eax
+; CHECK-NEXT: blcmskl %edi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
%t1 = xor i32 %t0, %a
@@ -406,7 +406,7 @@ define i32 @test_x86_tbm_blcmsk_u32(i32
define i32 @test_x86_tbm_blcmsk_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcmsk %edi, %eax
+; CHECK-NEXT: blcmskl %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -435,7 +435,7 @@ define i32 @test_x86_tbm_blcmsk_u32_z2(i
define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcmsk %rdi, %rax
+; CHECK-NEXT: blcmskq %rdi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
%t1 = xor i64 %t0, %a
@@ -445,7 +445,7 @@ define i64 @test_x86_tbm_blcmsk_u64(i64
define i64 @test_x86_tbm_blcmsk_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcmsk %rdi, %rax
+; CHECK-NEXT: blcmskq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -473,7 +473,7 @@ define i64 @test_x86_tbm_blcmsk_u64_z2(i
define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcs_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcs %edi, %eax
+; CHECK-NEXT: blcsl %edi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
%t1 = or i32 %t0, %a
@@ -483,7 +483,7 @@ define i32 @test_x86_tbm_blcs_u32(i32 %a
define i32 @test_x86_tbm_blcs_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcs_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcs %edi, %eax
+; CHECK-NEXT: blcsl %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -512,7 +512,7 @@ define i32 @test_x86_tbm_blcs_u32_z2(i32
define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blcs_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcs %rdi, %rax
+; CHECK-NEXT: blcsq %rdi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
%t1 = or i64 %t0, %a
@@ -522,7 +522,7 @@ define i64 @test_x86_tbm_blcs_u64(i64 %a
define i64 @test_x86_tbm_blcs_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blcs_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blcs %rdi, %rax
+; CHECK-NEXT: blcsq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -550,7 +550,7 @@ define i64 @test_x86_tbm_blcs_u64_z2(i64
define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blsfill_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsfill %edi, %eax
+; CHECK-NEXT: blsfilll %edi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, -1
%t1 = or i32 %t0, %a
@@ -560,7 +560,7 @@ define i32 @test_x86_tbm_blsfill_u32(i32
define i32 @test_x86_tbm_blsfill_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsfill_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsfill %edi, %eax
+; CHECK-NEXT: blsfilll %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, -1
@@ -589,7 +589,7 @@ define i32 @test_x86_tbm_blsfill_u32_z2(
define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blsfill_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsfill %rdi, %rax
+; CHECK-NEXT: blsfillq %rdi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, -1
%t1 = or i64 %t0, %a
@@ -599,7 +599,7 @@ define i64 @test_x86_tbm_blsfill_u64(i64
define i64 @test_x86_tbm_blsfill_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsfill_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsfill %rdi, %rax
+; CHECK-NEXT: blsfillq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, -1
@@ -627,7 +627,7 @@ define i64 @test_x86_tbm_blsfill_u64_z2(
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsic %edi, %eax
+; CHECK-NEXT: blsicl %edi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
%t1 = add i32 %a, -1
@@ -638,7 +638,7 @@ define i32 @test_x86_tbm_blsic_u32(i32 %
define i32 @test_x86_tbm_blsic_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsic %edi, %eax
+; CHECK-NEXT: blsicl %edi, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
@@ -670,7 +670,7 @@ define i32 @test_x86_tbm_blsic_u32_z2(i3
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsic %rdi, %rax
+; CHECK-NEXT: blsicq %rdi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
%t1 = add i64 %a, -1
@@ -681,7 +681,7 @@ define i64 @test_x86_tbm_blsic_u64(i64 %
define i64 @test_x86_tbm_blsic_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: blsic %rdi, %rax
+; CHECK-NEXT: blsicq %rdi, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
@@ -713,7 +713,7 @@ define i64 @test_x86_tbm_blsic_u64_z2(i6
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: t1mskc %edi, %eax
+; CHECK-NEXT: t1mskcl %edi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
%t1 = add i32 %a, 1
@@ -724,7 +724,7 @@ define i32 @test_x86_tbm_t1mskc_u32(i32
define i32 @test_x86_tbm_t1mskc_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: t1mskc %edi, %eax
+; CHECK-NEXT: t1mskcl %edi, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
@@ -757,7 +757,7 @@ define i32 @test_x86_tbm_t1mskc_u32_z2(i
define i64 @test_x86_tbm_t1mskc_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: t1mskc %rdi, %rax
+; CHECK-NEXT: t1mskcq %rdi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
%t1 = add i64 %a, 1
@@ -768,7 +768,7 @@ define i64 @test_x86_tbm_t1mskc_u64(i64
define i64 @test_x86_tbm_t1mskc_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: t1mskc %rdi, %rax
+; CHECK-NEXT: t1mskcq %rdi, %rax
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
@@ -801,7 +801,7 @@ define i64 @test_x86_tbm_t1mskc_u64_z2(i
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: tzmsk %edi, %eax
+; CHECK-NEXT: tzmskl %edi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
%t1 = add i32 %a, -1
@@ -812,7 +812,7 @@ define i32 @test_x86_tbm_tzmsk_u32(i32 %
define i32 @test_x86_tbm_tzmsk_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_tzmsk_u32_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: tzmsk %edi, %eax
+; CHECK-NEXT: tzmskl %edi, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
@@ -845,7 +845,7 @@ define i32 @test_x86_tbm_tzmsk_u32_z2(i3
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: tzmsk %rdi, %rax
+; CHECK-NEXT: tzmskq %rdi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
%t1 = add i64 %a, -1
@@ -856,7 +856,7 @@ define i64 @test_x86_tbm_tzmsk_u64(i64 %
define i64 @test_x86_tbm_tzmsk_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_tzmsk_u64_z:
; CHECK: # %bb.0:
-; CHECK-NEXT: tzmsk %rdi, %rax
+; CHECK-NEXT: tzmskq %rdi, %rax
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
@@ -889,7 +889,7 @@ define i64 @test_x86_tbm_tzmsk_u64_z2(i6
define i64 @test_and_large_constant_mask(i64 %x) {
; CHECK-LABEL: test_and_large_constant_mask:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $15872, %rdi, %rax # imm = 0x3E00
+; CHECK-NEXT: bextrq $15872, %rdi, %rax # imm = 0x3E00
; CHECK-NEXT: retq
entry:
%and = and i64 %x, 4611686018427387903
@@ -899,7 +899,7 @@ entry:
define i64 @test_and_large_constant_mask_load(i64* %x) {
; CHECK-LABEL: test_and_large_constant_mask_load:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: bextr $15872, (%rdi), %rax # imm = 0x3E00
+; CHECK-NEXT: bextrq $15872, (%rdi), %rax # imm = 0x3E00
; CHECK-NEXT: retq
entry:
%x1 = load i64, i64* %x
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Jan 11 22:21:36 2018
@@ -890,10 +890,10 @@
# CHECK-NEXT: xchgl %ebx, (%rax)
0xf2 0x87 0x18
-# CHECK: bextr $2814, %edi, %eax
+# CHECK: bextrl $2814, %edi, %eax
0x8f 0xea 0x78 0x10 0xc7 0xfe 0x0a 0x00 0x00
-# CHECK: blci %rdi, %rax
+# CHECK: blciq %rdi, %rax
0x8f 0xe9 0xf8 0x02 0xf7
# CHECK: vpcmov %xmm1, %xmm2, %xmm3, %xmm4
Modified: llvm/trunk/test/MC/X86/x86_64-tbm-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-tbm-encoding.s?rev=322354&r1=322353&r2=322354&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-tbm-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-tbm-encoding.s Thu Jan 11 22:21:36 2018
@@ -1,197 +1,197 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// bextri 32 reg
-// CHECK: bextr $2814, %edi, %eax
+// CHECK: bextrl $2814, %edi, %eax
// CHECK: encoding: [0x8f,0xea,0x78,0x10,0xc7,0xfe,0x0a,0x00,0x00]
bextr $2814, %edi, %eax
// bextri 32 mem
-// CHECK: bextr $2814, (%rdi), %eax
+// CHECK: bextrl $2814, (%rdi), %eax
// CHECK: encoding: [0x8f,0xea,0x78,0x10,0x07,0xfe,0x0a,0x00,0x00]
bextr $2814, (%rdi), %eax
// bextri 64 reg
-// CHECK: bextr $2814, %rdi, %rax
+// CHECK: bextrq $2814, %rdi, %rax
// CHECK: encoding: [0x8f,0xea,0xf8,0x10,0xc7,0xfe,0x0a,0x00,0x00]
bextr $2814, %rdi, %rax
// bextri 64 mem
-// CHECK: bextr $2814, (%rdi), %rax
+// CHECK: bextrq $2814, (%rdi), %rax
// CHECK: encoding: [0x8f,0xea,0xf8,0x10,0x07,0xfe,0x0a,0x00,0x00]
bextr $2814, (%rdi), %rax
// blcfill 32 reg
-// CHECK: blcfill %edi, %eax
+// CHECK: blcfilll %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xcf]
blcfill %edi, %eax
// blcfill 32 mem
-// CHECK: blcfill (%rdi), %eax
+// CHECK: blcfilll (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x0f]
blcfill (%rdi), %eax
// blcfill 64 reg
-// CHECK: blcfill %rdi, %rax
+// CHECK: blcfillq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xcf]
blcfill %rdi, %rax
// blcfill 64 mem
-// CHECK: blcfill (%rdi), %rax
+// CHECK: blcfillq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x0f]
blcfill (%rdi), %rax
// blci 32 reg
-// CHECK: blci %edi, %eax
+// CHECK: blcil %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0xf7]
blci %edi, %eax
// blci 32 mem
-// CHECK: blci (%rdi), %eax
+// CHECK: blcil (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0x37]
blci (%rdi), %eax
// blci 64 reg
-// CHECK: blci %rdi, %rax
+// CHECK: blciq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0xf7]
blci %rdi, %rax
// blci 64 mem
-// CHECK: blci (%rdi), %rax
+// CHECK: blciq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0x37]
blci (%rdi), %rax
// blcic 32 reg
-// CHECK: blcic %edi, %eax
+// CHECK: blcicl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xef]
blcic %edi, %eax
// blcic 32 mem
-// CHECK: blcic (%rdi), %eax
+// CHECK: blcicl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x2f]
blcic (%rdi), %eax
// blcic 64 reg
-// CHECK: blcic %rdi, %rax
+// CHECK: blcicq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xef]
blcic %rdi, %rax
// blcic 64 mem
-// CHECK: blcic (%rdi), %rax
+// CHECK: blcicq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x2f]
blcic (%rdi), %rax
// blcmsk 32 reg
-// CHECK: blcmsk %edi, %eax
+// CHECK: blcmskl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0xcf]
blcmsk %edi, %eax
// blcmsk 32 mem
-// CHECK: blcmsk (%rdi), %eax
+// CHECK: blcmskl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0x0f]
blcmsk (%rdi), %eax
// blcmsk 64 reg
-// CHECK: blcmsk %rdi, %rax
+// CHECK: blcmskq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0xcf]
blcmsk %rdi, %rax
// blcmsk 64 mem
-// CHECK: blcmsk (%rdi), %rax
+// CHECK: blcmskq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0x0f]
blcmsk (%rdi), %rax
// blcs 32 reg
-// CHECK: blcs %edi, %eax
+// CHECK: blcsl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xdf]
blcs %edi, %eax
// blcs 32 mem
-// CHECK: blcs (%rdi), %eax
+// CHECK: blcsl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x1f]
blcs (%rdi), %eax
// blcs 64 reg
-// CHECK: blcs %rdi, %rax
+// CHECK: blcsq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xdf]
blcs %rdi, %rax
// blcs 64 mem
-// CHECK: blcs (%rdi), %rax
+// CHECK: blcsq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x1f]
blcs (%rdi), %rax
// blsfill 32 reg
-// CHECK: blsfill %edi, %eax
+// CHECK: blsfilll %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xd7]
blsfill %edi, %eax
// blsfill 32 mem
-// CHECK: blsfill (%rdi), %eax
+// CHECK: blsfilll (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x17]
blsfill (%rdi), %eax
// blsfill 64 reg
-// CHECK: blsfill %rdi, %rax
+// CHECK: blsfillq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xd7]
blsfill %rdi, %rax
// blsfill 64 mem
-// CHECK: blsfill (%rdi), %rax
+// CHECK: blsfillq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x17]
blsfill (%rdi), %rax
// blsic 32 reg
-// CHECK: blsic %edi, %eax
+// CHECK: blsicl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xf7]
blsic %edi, %eax
// blsic 32 mem
-// CHECK: blsic (%rdi), %eax
+// CHECK: blsicl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x37]
blsic (%rdi), %eax
// blsic 64 reg
-// CHECK: blsic %rdi, %rax
+// CHECK: blsicq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xf7]
blsic %rdi, %rax
// t1mskc 32 reg
-// CHECK: t1mskc %edi, %eax
+// CHECK: t1mskcl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xff]
t1mskc %edi, %eax
// t1mskc 32 mem
-// CHECK: t1mskc (%rdi), %eax
+// CHECK: t1mskcl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x3f]
t1mskc (%rdi), %eax
// t1mskc 64 reg
-// CHECK: t1mskc %rdi, %rax
+// CHECK: t1mskcq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xff]
t1mskc %rdi, %rax
// t1mskc 64 mem
-// CHECK: t1mskc (%rdi), %rax
+// CHECK: t1mskcq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x3f]
t1mskc (%rdi), %rax
// tzmsk 32 reg
-// CHECK: tzmsk %edi, %eax
+// CHECK: tzmskl %edi, %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xe7]
tzmsk %edi, %eax
// tzmsk 32 mem
-// CHECK: tzmsk (%rdi), %eax
+// CHECK: tzmskl (%rdi), %eax
// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x27]
tzmsk (%rdi), %eax
// tzmsk 64 reg
-// CHECK: tzmsk %rdi, %rax
+// CHECK: tzmskq %rdi, %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xe7]
tzmsk %rdi, %rax
// tzmsk 64 mem
-// CHECK: tzmsk (%rdi), %rax
+// CHECK: tzmskq (%rdi), %rax
// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x27]
tzmsk (%rdi), %rax
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