[PATCH] D41969: [AMDGPU] stop image_store being moved illegally

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
tpr added reviewers: arsenm, nhaehnle, dstuttard.

A recent change
321556: AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
can allow the machine instruction scheduler to move an image store past
an image load using the same descriptor.

As a temporary workaround until we figure out what is going wrong with
alias analysis, this commit makes all image load and store instructions
volatile.


https://reviews.llvm.org/D41969

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/image-schedule.ll


Index: test/CodeGen/AMDGPU/image-schedule.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/image-schedule.ll
@@ -0,0 +1,55 @@
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
+
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target triple = "amdgcn--amdpal"
+
+; The first image store and the second image load use the same descriptor and
+; the same coordinate. Check that they do not get swapped by the machine
+; instruction scheduler.
+
+; GCN-LABEL: {{^}}_amdgpu_cs_main:
+; GCN: image_load
+; GCN: image_store
+; GCN: image_load
+; GCN: image_store
+
+define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32>) local_unnamed_addr #0 {
+.entry:
+  %6 = call i64 @llvm.amdgcn.s.getpc() #1
+  %7 = bitcast i64 %6 to <2 x i32>
+  %.0.vec.insert = insertelement <2 x i32> undef, i32 %2, i32 0
+  %.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %7, <2 x i32> <i32 0, i32 3>
+  %8 = bitcast <2 x i32> %.4.vec.insert to i64
+  %9 = inttoptr i64 %8 to [4294967295 x i8] addrspace(2)*
+  %10 = add <3 x i32> %3, %5
+  %11 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %9, i64 0, i64 32
+  %12 = bitcast i8 addrspace(2)* %11 to <8 x i32> addrspace(2)*, !amdgpu.uniform !10
+  %13 = load <8 x i32>, <8 x i32> addrspace(2)* %12, align 16
+  %14 = shufflevector <3 x i32> %10, <3 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %15 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %14, <8 x i32> %13, i32 15, i1 false, i1 false, i1 false, i1 false) #0
+  %16 = inttoptr i64 %8 to <8 x i32> addrspace(2)*
+  %17 = load <8 x i32>, <8 x i32> addrspace(2)* %16, align 16
+  call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %15, <2 x i32> %14, <8 x i32> %17, i32 15, i1 false, i1 false, i1 false, i1 false) #0
+  %18 = load <8 x i32>, <8 x i32> addrspace(2)* %16, align 16
+  %19 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %14, <8 x i32> %18, i32 15, i1 false, i1 false, i1 false, i1 false) #0
+  %20 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %9, i64 0, i64 64
+  %21 = bitcast i8 addrspace(2)* %20 to <8 x i32> addrspace(2)*, !amdgpu.uniform !10
+  %22 = load <8 x i32>, <8 x i32> addrspace(2)* %21, align 16
+  call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %19, <2 x i32> %14, <8 x i32> %22, i32 15, i1 false, i1 false, i1 false, i1 false) #0
+  ret void
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare i64 @llvm.amdgcn.s.getpc() #1
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
+
+; Function Attrs: nounwind
+declare void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone speculatable }
+attributes #2 = { nounwind readonly }
+
+!10 = !{}
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -579,6 +579,11 @@
   // Image load.
   case Intrinsic::amdgcn_image_load:
   case Intrinsic::amdgcn_image_load_mip:
+    // FIXME Need volatile to ensure machine instruction scheduler does not
+    // hoist a load above a store to the same descriptor. This could be because
+    // the alias analysis for image ops is faulty.
+    Info.flags |= MachineMemOperand::MOVolatile;
+    // fall through...
 
   // Sample.
   case Intrinsic::amdgcn_image_sample:
@@ -680,6 +685,10 @@
       CI.getArgOperand(2));
     Info.flags = MachineMemOperand::MOStore |
                  MachineMemOperand::MODereferenceable;
+    // FIXME Need volatile to ensure machine instruction scheduler does not
+    // hoist a load above a store to the same descriptor. This could be because
+    // the alias analysis for image ops is faulty.
+    Info.flags |= MachineMemOperand::MOVolatile;
     Info.align = 0;
     return true;
   }


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