[llvm] r322299 - [Hexagon] Impose limits on container sizes in HexagonGenInsert
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 10:02:13 PST 2018
Author: kparzysz
Date: Thu Jan 11 10:02:13 2018
New Revision: 322299
URL: http://llvm.org/viewvc/llvm-project?rev=322299&view=rev
Log:
[Hexagon] Impose limits on container sizes in HexagonGenInsert
With over 300k virtual registers, the size of the data exceeded 12GB.
Impose limits on how much information is collected.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=322299&r1=322298&r2=322299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Thu Jan 11 10:02:13 2018
@@ -55,6 +55,12 @@ static cl::opt<unsigned> VRegDistCutoff(
cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert "
"generation."));
+// Limit the container sizes for extreme cases where we run out of memory.
+static cl::opt<unsigned> MaxORLSize("insert-max-orl", cl::init(4096),
+ cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of OrderedRegisterList"));
+static cl::opt<unsigned> MaxIFMSize("insert-max-ifmap", cl::init(1024),
+ cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of IFMap"));
+
static cl::opt<bool> OptTiming("insert-timing", cl::init(false), cl::Hidden,
cl::ZeroOrMore, cl::desc("Enable timing of insert generation"));
static cl::opt<bool> OptTimingDetail("insert-timing-detail", cl::init(false),
@@ -86,6 +92,7 @@ namespace {
struct RegisterSet : private BitVector {
RegisterSet() = default;
explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {}
+ RegisterSet(const RegisterSet &RS) : BitVector(RS) {}
using BitVector::clear;
@@ -370,9 +377,11 @@ namespace {
class OrderedRegisterList {
using ListType = std::vector<unsigned>;
+ const unsigned MaxSize;
public:
- OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {}
+ OrderedRegisterList(const RegisterOrdering &RO)
+ : MaxSize(MaxORLSize), Ord(RO) {}
void insert(unsigned VR);
void remove(unsigned VR);
@@ -433,12 +442,17 @@ void OrderedRegisterList::insert(unsigne
Seq.push_back(VR);
else
Seq.insert(L, VR);
+
+ unsigned S = Seq.size();
+ if (S > MaxSize)
+ Seq.resize(MaxSize);
+ assert(Seq.size() <= MaxSize);
}
void OrderedRegisterList::remove(unsigned VR) {
iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
- assert(L != Seq.end());
- Seq.erase(L);
+ if (L != Seq.end())
+ Seq.erase(L);
}
namespace {
@@ -950,6 +964,9 @@ void HexagonGenInsert::collectInBlock(Ma
continue;
findRecordInsertForms(VR, AVs);
+ // Stop if the map size is too large.
+ if (IFMap.size() > MaxIFMSize)
+ return;
}
}
More information about the llvm-commits
mailing list