[PATCH] D41126: [SelectionDAG] Fixed f16-from-vector promotion problem

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:175
+      && Op.getValueType().getVectorNumElements() == 1)
+    Op = GetScalarizedVector(Op);
   EVT NewVT = N->getValueType(0).getVectorElementType();
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arsenm wrote:
> samparker wrote:
> > arsenm wrote:
> > > Can you add an assert that the v1 type isn't legal?
> > Hi,
> > The added assert is causing issues in our AArch64 tests... why is it necessary?
> It probably isn't necessary, but unlike the other operations handled here, it would make sense for bitcast to not separately scalarize its operand if v1 is a legal type. However, v1 as legal is a degenerate case which probably should not be allowed. It looks like AArch64 is using this as a hack for some reason with a FIXME about it.
Could you point me to this FIXME please? I'm still confused as to why we should prevent a scalar from being produced just because the vector is legal, is this because of how the legalizer is expected to operate?


Repository:
  rL LLVM

https://reviews.llvm.org/D41126