[llvm] r322265 - [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints

[Sander de Smalen via llvm-commits]

Author: s.desmalen
Date: Thu Jan 11 02:02:27 2018
New Revision: 322265

URL: http://llvm.org/viewvc/llvm-project?rev=322265&view=rev
Log:
[AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints

Summary: Patch [3/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo

Reviewed By: rengolin, fhahn

Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41447

Modified:
    llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s
    llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s

Modified: llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s?rev=322265&r1=322264&r2=322265&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s Thu Jan 11 02:02:27 2018
@@ -51,4 +51,27 @@ add z30.s, p8/m, z30.s, z13.s
 add z29.d, p8/m, z29.d, z8.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: add z29.d, p8/m, z29.d, z8.d
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+add z19.b, p4/m, z20.b, z13.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: add z19.b, p4/m, z20.b, z13.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add z9.h, p3/m, z10.h, z28.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: add z9.h, p3/m, z10.h, z28.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add z5.s, p3/m, z6.s, z18.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: add z5.s, p3/m, z6.s, z18.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add z9.d, p4/m, z10.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: add z9.d, p4/m, z10.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

Modified: llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s?rev=322265&r1=322264&r2=322265&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s Thu Jan 11 02:02:27 2018
@@ -52,3 +52,26 @@ sub z29.d, p8/m, z29.d, z3.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: sub z29.d, p8/m, z29.d, z3.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+sub z25.b, p4/m, z26.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sub z25.b, p4/m, z26.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub z29.h, p6/m, z30.h, z20.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sub z29.h, p6/m, z30.h, z20.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub z14.s, p2/m, z15.s, z21.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sub z14.s, p2/m, z15.s, z21.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub z2.d, p5/m, z3.d, z11.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sub z2.d, p5/m, z3.d, z11.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: